Commit graph

17572 commits

Author SHA1 Message Date
Kuldeep Singh
e0152dbed6 net: pfe_eth: Use spi_flash_read API to access flash memory
Current PFE firmware access spi-nor memory directly. New spi-mem
framework does not support direct memory access. So, let's use
spi_flash_read API to access memory instead of directly using it.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Vladimir Oltean
e7005b3e80 fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delays
Communication with some SPI slaves just won't cut it if these delays
(before the beginning, and after the end of a transfer) are not added to
the Chip Select signal.

These are a straight copy from Linux:
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
drivers/spi/spi-fsl-dspi.c

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:26 +05:30
Tom Rini
ada61f1ee2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Fix SiFive HiFive Unleashed board booting failure problem.
- Enable SiFive fu540 PWM driver.
- Support SiFive fu540: SPI boot.
- Update OpenSBI used for RISC-V CI testing.
- Revert "riscv: Allow use of reset drivers".
- Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"".
- sysreset: syscon:
        - Don't assume default value for offset and mask property.
        - Support value property.
- qemu: Add syscon reboot and poweroff support.
- Fix SIFIVE debug serial dependency.
- Fix linking error when building u-boot-spl with no SMP support.
- AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg.
- Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi
- SiFive fu540 avoid using hardcoded ram base and size.
2020-07-24 08:43:08 -04:00
Tom Rini
7208396bbf Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"
This reverts commit 5d3a21df66, reversing
changes made to 56d37f1c56.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24 08:42:06 -04:00
Bin Meng
ecb70bdb9f ram: sifive: Avoid using hardcoded ram base and size
At present the SiFive FU540 RAM driver uses hard-coded memory base
address and size to initialize the DDR controller. This may not be
true when this driver is used on another board based on FU540.

Update the driver to read the memory information from DT and use
that during the initialization.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24 14:56:29 +08:00
Michal Simek
27b4a4abe6 serial: Fix SIFIVE debug serial dependency
The commit 4cc24aeaf4 ("serial: Add missing Kconfig dependencies for
debug consoles") has added incorrect dependency for SIFIVE debug uart which
should depend on SIFIVE driver instead of PL01x.

Fixes: 4cc24aeaf4 ("serial: Add missing Kconfig dependencies for debug consoles")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-07-24 14:56:04 +08:00
Bin Meng
9cdfade85e sysreset: syscon: Support value property
Per the DT binding, <mask> and <value> property can have either one
or both, and if <value> is missing, <mask> should be used, which is
what current U-Boot sysreset_syscon driver supports.

This adds support to the <value> property to the driver, and <mask>
semantics is updated to really be a mask to the value if both exist.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24 14:55:49 +08:00
Bin Meng
1ce8182b0f sysreset: syscon: Don't assume default value for offset and mask property
Per the DT binding, <offset> is a required property. Let's abort
the probe if it is missing. For the <mask> property, current codes
assume a default value of zero, which is not correct either.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24 14:55:43 +08:00
Tom Rini
5d3a21df66 binman support for FIT
new UCLASS_SOC
 patman switch 'test' command
 minor fdt fixes
 patman usability improvements
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAl8V+WQRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIrebNgAgAmgHHPakg1fkJT8xZkbPD53r21t5fkF7h
 JTLVU93BKfC+Zz2bbizCEkCl9L9bdHSaSzJY5rb07E24yV/zwDcIkRApCmkDjVHN
 EHOb0P36Ht9acowSd5kN66wd2z0Q/V+7lfEdB6Adtprh0vVaWIKYtLPxogpRv6k9
 l/CaGsBCwvupmPeHZcE3pVQlflbKyYzp62VObEBI4RIJLisvDXaPRUcBa4vz904P
 yu0baIYW8hWBcZhb0Lkex/9x7ys2T1bnnw8G7WL05GtHSZfVvT46Y70o+3i5ycBh
 GAI93Lx4r1gCjol9LVE4i1bewbPiMqyNXOtKGPRt/IIvYI4HZ67lFA==
 =YIpM
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm

binman support for FIT
new UCLASS_SOC
patman switch 'test' command
minor fdt fixes
patman usability improvements
2020-07-23 15:56:06 -04:00
Tom Rini
95fc1f1647 Merge tag 'u-boot-rockchip-20200722' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New rk3326 board: Hardkernel Odroid Go2;
- Update board config and dts for RockPI 4/N8/N10;
- Update led boot on support for roc-rk3399-pc;
- Enable SPI Flash suppor for rk3328 rock64 board;
- Update rockchip pcie phy to use generic framework;
2020-07-22 11:30:52 -04:00
Jagan Teki
ad415c80a5 pci: rockchip: Drop legacy PHY driver
Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:49 +08:00
Jagan Teki
ce920e0e56 pci: rockchip: Switch to generic-phy
Now, we have a PCIe PHY driver as part of the Generic
PHY framework. Let's use it instead of legacy PHY driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:47 +08:00
Jagan Teki
7bdeb4ef4c phy: Add Rockchip PCIe PHY driver
Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:42 +08:00
Kever Yang
b32858ca51 rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not set
The empty function define should not be in the header file, or else the
build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG
is disabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:33 +08:00
Jagan Teki
40794c825f ram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUG
Right now all these debug statements are printing on the
console to make sure proper dram initialization happens.  

Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful
and work like before since the RAM_ROCKCHIP_DEBUG is by
default yet.

No functionality changes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:28 +08:00
Jagan Teki
304eaae36b ram: rk3399: Drop debug stride in driver
stride debug is already present in sdram_common.c via
RAM_ROCKCHIP_DEBUG.

So, drop the redundant debug stride code in rk3399 driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:23 +08:00
Johannes Krottmayer
e93d2f4e96 drivers: spi: rk_spi: Add support for RK3328
Add support for the RK3328 SPI controller

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:03 +08:00
Johannes Krottmayer
19933b66f4 drivers: clk: rockchip: clk_rk3328: Add SPI support
Add SPI support for the RK3328 clock driver

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:00 +08:00
Masahiro Yamada
60e7fa8b3b treewide: convert devfdt_get_addr() to dev_read_addr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  expression dev;
  @@
  -devfdt_get_addr(dev)
  +dev_read_addr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20 11:37:47 -06:00
Masahiro Yamada
6f25e274da treewide: remove (phys_addr_t) casts from devfdt_get_addr()
This cast is unneeded.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20 11:37:47 -06:00
Masahiro Yamada
3c12c62ba5 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()
Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.

One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:

    priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
    if (!priv->regs)
            return -EINVAL;

devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.

dev_read_addr_ptr() returns NULL on error, so this error check
will work.

I generated this commit by the following command:

 $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
   xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'

I manually fixed drivers/usb/host/ehci-mx6.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20 11:37:47 -06:00
Dave Gerlach
527be812a8 dm: soc: Introduce soc_ti_k3 driver for TI K3 SoCs
Introduce an soc_ti_k3_driver that allows identification and selection
of SoC specific data based on the JTAG ID register for device
identification, as described for AM65x[0] and J721E[1] devices.

[0] http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
[1] http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20 11:37:47 -06:00
Dave Gerlach
fbde39f417 test: Add tests for SOC uclass
Add a sandbox SOC driver, and some tests for the SOC uclass.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20 11:37:47 -06:00
Dave Gerlach
6426a26f4c dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matching
Introduce UCLASS_SOC to be used for SOC identification and attribute
matching based on the SoC ID info. This allows drivers to be provided
for SoCs to retrieve SoC identifying information and also for matching
device attributes for selecting SoC specific data.

This is useful for other device drivers that may need different
parameters or quirks enabled depending on the specific device variant in
use.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20 11:37:47 -06:00
Simon Glass
f07e58b878 cpu: Convert the methods to use a const udevice *
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-20 11:37:47 -06:00
Simon Glass
5d9dc917e1 dm: core Fix long line in device_bind_common()
Fix an over-length line in this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 11:37:47 -06:00
Shivamurthy Shastri
fe48d4f996 mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies
Add device table for new Micron SPI NAND devices, which have multiple
dies.

Also, enable support to select the dies.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20 22:29:18 +05:30
Shivamurthy Shastri
1f4836b0c9 mtd: spinand: micron: Add M70A series Micron SPI NAND devices
Add device table for M70A series Micron SPI NAND devices.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20 22:28:54 +05:30
Shivamurthy Shastri
720fcb27e0 mtd: spinand: micron: identify SPI NAND device with Continuous Read mode
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.

Hence, we disable the feature at probe time.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20 22:28:33 +05:30
Shivamurthy Shastri
5cf049c00a mtd: spinand: micron: Add new Micron SPI NAND devices
Add device table for M79A and M78A series Micron SPI NAND devices.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20 22:28:09 +05:30
Shivamurthy Shastri
92fc25df2e mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage
details as a comment.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20 22:27:53 +05:30
Shivamurthy Shastri
1527ec410c mtd: spinand: micron: Generalize the OOB layout structure and function names
In order to add new Micron SPI NAND devices, we generalized the OOB
layout structure and function names.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20 22:27:29 +05:30
Simon Glass
d2ee543ae2 dm: core: Don't show an ACPI warning if there is no ordering
Some boards don't care about the ordering of ACPI code fragments. Change
the warning to a debug message.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:42 +08:00
Stefan Roese
59aea37abf sysreset: Add Octeon sysreset driver
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-07-18 14:23:25 +02:00
Martin Kaistra
892d461735 mtd: mtdpart: use uint64_t instead of int for cur_off
The types of "offset" and "size" of "struct mtd_partition" are uint64_t,
while mtd_parse_partitions() uses int to work with these values. When
the offset reaches 2GB, it is interpreted as a negative value, which
leads to error messages like

mtd: partition "<partition name>" is out of reach -- disabled

eg. when using the "ubi part" command.

Fix this by using uint64_t for cur_off and cur_sz.

Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de>
Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-07-17 10:47:19 -04:00
Masahiro Yamada
bb5a2cf9f9 treewide: convert bd_t to struct bd_info manually
Some code was not converted by coccinelle, somehow.

I manually fixed up the remaining, and comments, README docs.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
[trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and
        include/fdt_support.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-17 10:46:44 -04:00
Masahiro Yamada
b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00
Tom Rini
e6676a34c4 Convert CONFIG_MXC_UART to Kconfig
This converts the following to Kconfig:
   CONFIG_MXC_UART

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-07-17 08:47:29 -04:00
Tom Rini
7c3cc6f106 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- New timer API to allow delays with a 32-bit microsecond timer
- Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core
- x86: Enable ACPI table generation by default
- x86: Enable the copy framebuffer on Coral
- x86: A few fixes to FSP2 with ApolloLake
- x86: Drop setup_pcat_compatibility()
- x86: Primary-to-Sideband Bus minor fixes
2020-07-17 08:04:48 -04:00
Tom Rini
42e7659db0 i.MX for 2020.10
----------------
 
 - i.MX DDR driver fix/update for i.MX8M
 - i.MX pinctrl driver fix.
 - Use arm_smccc_smc to remove imx sip function
 - i.MX8M clk update
 - support booting aarch32 kernel on aarch64 hardware
 - fused part support for i.MX8MP
 - imx6: pcm058 to DM
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCXxCxWw8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76bPyACcDZ8gD9jf1P/Zh+7kqrGdIWwURF8AnAiEtNnu
 FhE/WQQj4mAEWE4F2bFE
 =7ceG
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20200716' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.10
----------------

- i.MX DDR driver fix/update for i.MX8M
- i.MX pinctrl driver fix.
- Use arm_smccc_smc to remove imx sip function
- i.MX8M clk update
- support booting aarch32 kernel on aarch64 hardware
- fused part support for i.MX8MP
- imx6: pcm058 to DM

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785
2020-07-17 08:04:28 -04:00
Simon Glass
d40d2c5706 acpi: Enable ACPI table generation by default on x86
This should ideally be used by all x86 boards in U-Boot. Enable it by
default. If some boards don't use it, the cost is small.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
b95611f67e x86: apl: Fix save/restore of ITSS priorities
The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.

Fix this by allocating space in the relocated memory for the ITSS data.
Save it there and access it from the driver after relocation.

This fixes interrupt handling on coral.

Also drop the log_msg_ret() in irq_first_device_type() since this function
can be called speculatively in places where we are not sure if there is
an interrupt controller of that type. The resulting log errors are
confusing when there is no error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
11e27ae92b pmc: Move common registers to the header file
These registers need to be accesses from ACPI code, so move them to the
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
6d349e2e43 p2sb: Add a method to hide the bus
The P2SB bus needs to be hidden in some cases so that it does not get
auto-configured by Linux. Add a method for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
4b0ec52b9e i2c: designware_i2c: Support ACPI table generation
Update the PCI driver to generate ACPI information so that Linux has the
full information about each I2C bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Correct one typo in dw_i2c_gen_speed_config() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
c61c8efd47 i2c: Add log_ret() on error
Add a few of these calls to make it easier to see where an error occurs,
if CONFIG_LOG_ERROR_RETURN is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-07-17 14:32:24 +08:00
Simon Glass
767abfc6ce i2c: designware_i2c: Add a little more debugging
Add debugging for a few more values and also use log to show return values
when something goes wrong. This makes it easier to see the root cause.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-07-17 14:32:24 +08:00
Simon Glass
43ee86cc4b x86: gpio: Add support for obtaining ACPI info for a GPIO
Implement the method that converts a GPIO into the form used by ACPI, so
that GPIOs can be added to ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
59cf26480b x86: pinctrl: Drop the acpi_path member
This is in the device tree now, so drop the unnecessary field here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
6b651486f5 x86: pinctrl: Set up itss in the probe() method
At present the itss is probed in the ofdata_to_platdata() method. This is
incorrect since itss is a child of p2sb which itself needs to probe the
pinctrl device. This means that p2sb is effectively not probed when the
itss is probed, so we get the wrong register address from p2sb.

Fix this by moving the itss probe to the correct place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00