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8 commits

Author SHA1 Message Date
Philippe Schenker
f72e48ba4d board: apalis_imx6: Add KSZ9131 phy skew settings
This patch adds skew register settings for KSZ9131. It checks first
which phy is on the board and then applies the correct skew settings.

Skew settings calculation for the KSZ9131:
The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All
PCB traces where routed exactly the same length so we can calculate
the skew settings without taking the length into consideration. The
traces are all length matched.

RXC skew (PHY to MAC):
- We use the 2ns DLL controlled delay on the PHY
- We do not use the skew registers

This results in the following values:

		RXC
PHY fixed Delay	2000ps
PHY Added Delay	0ps
T_setup_R min	2.00ns
T_setup_R typ	2.00ns
T_setup_R max	2.00ns
T_hold_R min	1.60ns
T_hold_R typ	2.00ns
T_hold_R max	2.40ns

That means we are well within RGMII specs.

TXC skew (MAC to PHY):
- We use the 2ns DLL controlled delay on the PHY
- We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew
  register in a resulting ~1.4ns delay.

This results in the following values under consideration of the
tolerances:

		TXC min	TXC typ	TXC max
MAC min		-100ps	-100ps	-100ps
MAC max		900ps	900ps	900ps
PHY fixed Delay	2000ps	2000ps	2000ps
PHY added Delay	-340ps	-600ps	-859ps
T_setup_T min	1.56ns	1.30ns	1.04ns
T_setup_T typ	2.06ns	1.80ns	1.54ns
T_setup_T max	2.56ns	2.30ns	2.04ns
T_hold_T min	1.04ns	1.30ns	1.56ns
T_hold_T typ	1.94ns	2.20ns	2.46ns
T_hold_T max	2.84ns	3.10ns	3.36ns

This shows that T_hold_T min and T_setup_T min times are out of spec
for RGMII timing. However the KSZ9131 has a minimal value for this time
of 0.8ns which is met under all circumstances.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01 13:46:22 +02:00
Philippe Schenker
c51eef5924 net: phy: micrel: Add basic support for KSZ9131
This adds basic support for the new Micrel KSZ9131 phy.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01 13:46:22 +02:00
Philippe Schenker
0861aa8fed net: phy: micrel: Use defines for PHY_IDs and MASK
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01 13:46:22 +02:00
Ash Charles
f018545ef7 net: phy: micrel: center FLP burst timing at 16ms
Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms
specified by the IEEE802.3 standard from the chip's default of 8ms.

For more details, see the "Auto-Negotiation Timing" section of the
KSZ9031RNX datasheet.

[1] https://patchwork.kernel.org/patch/6558371/

Signed-off-by: Ash Charles <ash.charles@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-07 11:28:16 -06:00
Otavio Salvador
f02229021d cgtqmx6eval: Add Ethernet support
cgtqmx6eval can be populated with a AR8035 or KSZ9031 depending on the
board revision.

Add Ethernet support.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2015-09-02 15:26:12 +02:00
Stefano Babic
71817a16f1 phy: add missing constants for Micrel KSZ9031
Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:51 -06:00
SARTRE Leo
42a7cb50a9 net: phy: supplement support for Micrel's KSZ9031
Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read

Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
2013-06-24 19:11:16 -05:00
Troy Kisky
8682aba7da net: phy: add support for Micrel's KSZ9021
Add the gigabit phy KSZ9021.
Also, add function ksz9021_phy_extended_write
/_read for access to the phys extended registers.
The environment variable "disable_giga"
can be used to disable 1000baseTx.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2012-02-27 21:19:25 +01:00