Commit graph

71222 commits

Author SHA1 Message Date
Biwen Li
0c6dd90119 configs: ls1012afrwy: enable CMD_GPIO
Enable CMD_GPIO for ls1012afrwy

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:21 +05:30
Biwen Li
d58ea6380e configs: ls1021aqds: enable CONFIG_MPC8XXX_GPIO
Enable CONFIG_MPC8XXX_GPIO for board ls1021aqds

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:21 +05:30
Biwen Li
7c1f095aca configs: ls1021atwr: enable CONFIG_MPC8XXX_GPIO
Enable CONFIG_MPC8XXX_GPIO for board ls1021atwr

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:21 +05:30
Biwen Li
0077d711c9 configs: ls1046a: enable MPC8XXX_GPIO
Enable MPC8XXX_GPIO for SoC LS1046A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:21 +05:30
Biwen Li
2a95d7c76f configs: lx2160a: enable CONFIG_MPC8XXX_GPIO
Enable CONFIG_MPC8XXX_GPIO for SoC LX2160A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:21 +05:30
Biwen Li
04f26d616d configs: ls208xa: enable CONFIG_MPC8XXX_GPIO
Enable CONFIG_MPC8XXX_GPIO for LS208xA

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:21 +05:30
Biwen Li
97e8120850 configs: ls1088a: enable CONFIG_MPC8XXX_GPIO
Enable CONFIG_MPC8XXX_GPIO for LS1088A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:21 +05:30
Biwen Li
90281f4c27 configs: ls1028a: enable CONFIG_MPC8XXX_GPIO
Enable CONFIG_MPC8XXX_GPIO for SoC LS1028A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
be7b6d5944 configs: ls1043a: enable CONFIG_MPC8XXX_GPIO
Enable CONFIG_MPC8XXX_GPIO for SoC LS1043A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
c5d0bd5dc8 configs: ls1012a: enable CONFIG_MPC8XXX_GPIO
Enable CONFIG_MPC8XXX_GPIO for SoC LS1012A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
eeeab2750e arm64: dts: ls208xa: add gpio node
Add gpio node for SoC LS208xA

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
d62cbea84a arm64: dts: ls1088a: add gpio node
Add gpio node for SoC LS1088A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
b7ddedfab5 arm64: dts: ls1046a: add gpio node
Add gpio node for SoC LS1046A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
b609f1ad04 arm64: dts: ls1043a: add gpio node
Add gpio node for SoC LS1043A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:20 +05:30
Biwen Li
f9428d761b arm64: dts: ls1028a: add gpio node
Add gpio node for SoC LS1028A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Biwen Li
5609300521 arm64: dts: ls1012a: add gpio node
Add gpio node for SoC LS1012A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Biwen Li
2b3393cb3c arm: dts: ls1021a: add gpio node
Add gpio node for SoC LS1021A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Biwen Li
781188097d gpio: mpc8xxx_gpio: Fix for litte endian
Update gpio driver to use same logic for big-endian and little-endian

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Hou Zhiqiang
c9cd2a31cc configs: T1042: Drop the CONFIG_VIDEO
Drop the CONFIG_VIDEO to fix the following build warning.
===================== WARNING ======================
This board does not use CONFIG_DM_VIDEO Please update
the board to use CONFIG_DM_VIDEO before the v2019.07 release.
UPD     include/generated/dt.h
Failure to update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
UPD     include/generated/timestamp_autogenerated.h
====================================================

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Priyanka Jain
43d1d391f6 mpc8xxx: fsl_pamu: Update data type in config_pamu
Update data type of '1' to '1ull' in below assignment
size = 1ull << sizebit;

to fix incorrect assignment issue.
e.g: when sizebit was 31, 0x80000000 got sign extended to
0xffffffff_80000000

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reported-by: Dean Saridakis <dean.saridakis@baesystems.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Hou Zhiqiang
19dba8bf9f armv7: ls102xa: Enable I-Cache to speed up the boot time
Enable the I-Cache to speed up the boot time, especailly for the NOR
boot, currently it takes about 15 seconds from power up to the U-Boot
prompt, and with the I-Cache enabled it only takes around 2.5 seconds.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:19 +05:30
Aleksandar Gerasimovski
a1f57c3933 board/km: move km i2c deblock declarations to a km/common.h
Cleanup, move the declarations to keymile/common.h instead declaring them
per-board config.h

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Hou Zhiqiang
d167667d1b pci: kconfig: layerscape: Change LX2162A PCIe node compatible string
LX2162A is not like LX2160A which has different PCIe controller
in rev1 and rev2 silicon. It supports only one configuration of
PCIe controller, which is same as LS2088A. So update PCIe
compatible string same as LS2088A.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Tested-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Hou Zhiqiang
584107337b pci: layerscape: Remove the shadow SVR definitions
This patch moves the SVR definitions to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Mathew McBride
fd20097336 spi: fsl_qspi: apply the same settings for LS1088 as LS208x
The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL
workaround as the LS208x and also has a 64 byte TX buffer.

With the previous settings SPI-NAND reads over AHB were
corrupted.

Fixes: 91afd36f38 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API")
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Mathew McBride
6b4eb604ea spi: fsl_qspi: Ensure width is respected in spi-mem operations
Adapted from kernel commit b0177aca7aea
From: Michael Walle <michael@walle.cc>

Make use of a core helper to ensure the desired width is respected
when calling spi-mem operators.

Otherwise only the SPI controller will be matched with the flash chip,
which might lead to wrong widths. Also consider the width specified by
the user in the device tree.

Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller")
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot]
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Mathew McBride
af6266c1c2 mem: spi-mem: add declaration for spi_mem_default_supports_op
spi_mem_default_supports_op is used internally by controller
drivers to verify operation semantics are correct.

It is used internally inside spi-mem but has not (in U-Boot)
been declared in spi-mem.h for external use.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Niel Fourie
37bfd9cb50 PowerPC: keymile: Add support for kmcent2 board
Add basic support for the Hitachi Power Grids kmcent2 board, based
on the NXP QorIQ T1040 SoC.

Signed-off-by: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
[Fixed blank line at EOF errors]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Niel Fourie
df86d324c7 keymile: common: update to set_env_hex(), fix "pram" radix
Replace instances of sprintf()/set_env() for setting hexadecimal
values with set_env_hex().

In set_km_env() the "pram" variable was set to an hexadecimal
value, while initr_mem() expects an unsigned decimal, so use
set_env_ulong() instead.

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:17 +05:30
Niel Fourie
c1a215b455 PowerPC: dts: Pulled in kmcent2 dts files from Linux 5.10
Pulled in the kmcent2.dts and all its dependents from Linux 5.10,
commit 2c85ebc57b3e upstream. Replaced the license text with
SPDX License Identifiers.

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:17 +05:30
Aleksandar Gerasimovski
e081d9441e board/km/common: fix pnvramaddr and varaddr
Take into account SDRAM_BASE address when calculating pnvramaddr and
varaddr offsets.
Up to now Keymile designs had SDRAM_BASE equal to zero and the offsets
where calculated correctly, this fix is for the upcoming designs that
have SDRAM_BASE different then zero.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:17 +05:30
Aleksandar Gerasimovski
d141f4b298 keymile: common: qrio: print QRIO id and revision number
Add show_qrio function to print chip id and revision information.
There are already multiple QRIO chip versions available and the upcoming
designs may want to show used version.

Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:17 +05:30
Aleksandar Gerasimovski
b99cc27111 board: keymile: common: fix qrio compilation for arm
This patch is fixing qrio driver compilation for ARM architecture:
- It includes asm/io.h for in_/out_ access
- It use correct names for set/clear_bits as defined in linux/bitops.h

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:16 +05:30
Wasim Khan
67477bd0ac armv8: lx2: SVR_SOC_VER: Mask CAN_FD and security bit
Multiple LX2(LX2160A/LX2162A SoC) personality variants
exists based on CAN-FD and security bit in SVR.

Currenly SVR_SOC_VER mask only security bit.
Update SVR_SOC_VER to mask CAN_FD and security bit
for LX2 products.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:16 +05:30
Nipun Gupta
3dbc47c9e5 armv8: ls1028a: fix stream id allocation
When A-050382 errata is enabled, ECAM and EDMA have
conflicting stream id 40. This patch fixes the same.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Reviewed-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:16 +05:30
Michael Walle
805b2423b4 board: sl28: add SATA support
Enable SATA support. Although not supported by the usual SATA pins on
the SMARC baseboard connector, SATA mode is supported on a PCIe lane.
This way one can use a mSATA card in a Mini PCI slot.

We need to invert the received data because in this mode the polarity of
the SerDes lane is swapped. Provide a fixup in board_early_init_f() for
the SPL. board_early_init_f() is then not common between SPL and u-boot
proper anymore, thus common.c is removed, as it just contained said
function.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:16 +05:30
Michael Walle
b463010be0 board: sl28: add network variant 2 support
Although this variant has two external network ports, they are not (yet)
supported by the bootloader because they are connected via an internal
network switch. Otherwise its the same as the other variants.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:16 +05:30
Michael Walle
4029d356e6 board: sl28: add network variant 1 support
This variant has one network port connected via RGMII and doesn't have
any TSN capabilities out-of-the-box. Instead it has all four SerDes
lanes available for customer use.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Michael Walle
feed9008b3 board: sl28: move ethernet aliases to variant specific dtsi
The variants differ in their network configuration. Move the first two
network aliases to the proper variant device tree includes. This is in
prepartion for variant 1 and 2 support which has a different network
port mapping. The network aliases for the two internal ports will stay
in the common dtsi because they are present on all board variants.

This might leave a hole if there is no ethernet1 alias. This is
intended.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Ye Li
440b28a8c6 net: eqos: Reduce the MDIO wait time
Current MDIO wait time is too long, which introduce long delay when
PHY negotiation register checking. Reduce it to 10us

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <Fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Zhao Qiang
905c8e649e armv8: dts: fsl-lx2162a: add dspi node into qds dts
Add dspi node into lx2162aqds device tree

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Wasim Khan
cbfa8f7c7a armv8: lx2162aqds: disable non existing pcie controllers
disable non existing pcie controllers on lx2162aqds

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:15 +05:30
Biwen Li
166e40bda6 configs: ls1088aqds: add COMMON_ENV to fix distroboot
Add COMMON_ENV(kernelheader_addr_r, fdtheader_addr_r,
kernel_addr_r, fdt_addr_r, load_addr)
to fix a bug that failed to boot to ubuntu
Failed log as follows,
	## Executing script at 80000000
	load - load binary file from a filesystemUsage:
	load <interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]]
	    - Load binary file filename from partition part on device
	       type interface instance dev to address addr in memory.
	      bytes gives the size to load in bytes.
	      If bytes is 0 or omitted, the file is read until the end.
	      pos gives the file byte position to start reading from.
	      If pos is 0 or omitted, the file is read from the start.
	...
	Bad Linux ARM64 Image magic!
	SCRIPT FAILED: continuing...

Signed-off-by: Biwen Li <biwen.li@nxp.com>
[Updated description]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:14 +05:30
Ioana Ciornei
64a0fb4cc3 net: memac_phy: add a timeout to MDIO operations
We have encountered circumstances when a board design does not include
pull-up resistors on the external MDIO buses which are not used. This
leads to the MDIO data line not being pulled-up, thus the MDIO controller
will always see the line as busy.

Without a timeout in the MDIO bus driver, the execution is stuck in an
infinite loop when any access is initiated on that external bus.

Add a timeout in the driver so that we are protected in this
circumstance. This is similar to what is being done in the Linux
xgmac_mdio driver.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:14 +05:30
Michael Walle
46fdf763b8 board: kontron: disable flash unlock all
Although the status register is protected by the hardware write
protection, there is a hardware jumper to disable that hardware write
protection. Thus if a user would set this jumper any u-boot start would
disable the write protection altogether.

Circumvent that by not disabling the write protection in the first
place.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:14 +05:30
Michael Walle
5d867bcc23 mtd: spi-nor: add unlock all config option
Provide an explicit configuration option to disable default "unlock all"
of any flash chip which supports locking. It doesn't make sense to
automatically unprotect the entire flash on each u-boot startup if the
block protection bits are actually used.

Traditionally, the unlock was there to be able to write to flash devices
which powered-up with the block protection bits set. Over time this
feature creeped into all flash devices which support locking.

For a more detailed description and discussion see:
https://lore.kernel.org/linux-mtd/20201203162959.29589-8-michael@walle.cc/

Keep things simple in u-boot and just provide a configration option to
disable this behavior which can be set per board.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:13 +05:30
Baruch Siach
24a0f8cfe5 mmc: mv_sdhci: parse device-tree entry
Call mmc_of_parse() so that generic DT properties like 'non-removable'
are taken into account.

This fixes boot on Clearfog with eMMC on SOM that requires the
non-removable property.

Reported-by: Thorsten Spille <thorsten_spille@netcor.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2021-02-08 08:53:14 +01:00
Konstantin Porotchkin
6e2748452a arm: mvebu: Espressobin: Set the maximum slave SPI speed to 40MHz
While the SPI controller speed is defined by DTS, the maximum
slave speed (connected devices) is limited by the pre-defined
configuration value CONFIG_SF_DEFAULT_SPEED to 1MHz
This patch increases this maximum SPI slave device speed to 40MHz

Change-Id: I0d1239bd8a2061c66725c2c227c1e1f49c92c29e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/59516
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
[pali: Set CONFIG_SF_DEFAULT_SPEED via defconfig]
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-08 08:53:14 +01:00
Pali Rohár
32771530e6 cmd: mvebu/bubt: Fix default options in help
Default options depends on compile time defines.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-08 08:53:14 +01:00
Stefan Roese
61b70422c3 arm: mvebu: theadorable: Set deephasis bit in PCIe configs very early
Testing has shown, that the quality of the PCIe signals and also the
stability of correct link establishment on the 2 PCIe ports is better,
when the deemphasis bit is set in the PCIe config register.

This needs to be done very early, even before the SERDES setup code is
run. This way, the first link will already be established with this
setup.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-02-08 08:53:14 +01:00