The CS_AUTOBOOT configurations have been broken for a long time.
Kshitij Gupta is no longer at TI making these broken and orphaned
boards, so remove.
Signed-off-by: Tom Rini <trini@ti.com>
Fix:
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Tom Rini <trini@ti.com>
Fix:
beagle.c:257:13: warning: function declaration isn't a prototype
[-Wstrict-prototypes]
beagle.c:257:13: warning: function declaration isn't a prototype
[-Wstrict-prototypes]
Also make beagle_dvi_pup() checkpatch clean, fix:
ERROR: open brace '{' following function declarations go on the
next line
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Tom Rini <trini@ti.com>
Add basic i2c driver for Tegra2 with 8- and 16-bit address support.
The driver requires CONFIG_OF_CONTROL to obtain its configuration
from the device tree.
(Simon Glass: sjg@chromium.org modified for upstream)
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add U-Boot's peripheral clock information to the Tegra20 device tree file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This enables I2C on Seaboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra 2x SOC has four ports, so define TEGRA_I2C_NUM_CONTROLLERS
in the shared config file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This enables I2C on all Nvidia boards including Seaboard and
Harmony.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
I2C ports have a 16-bit clock divisor. Add code to handle this special
case so that I2C speeds below 150KHz are supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some devices can deal with multiple compatible properties. The devices
need to know which nodes to bind to which features. For example an
I2C driver which supports two different controller types will want to
know which type it is dealing with in each case.
The new fdtdec_add_aliases_for_id() function deals with this by allowing
the driver to search for additional compatible nodes for a different ID.
It can then detect the new ones and perform appropriate processing.
Another option considered was to return a tuple (node offset, compat id)
and have the function be passed a list of compatible IDs. This is more
overhead for the common case though. We may add such a function later if
more drivers in U-Boot require it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change this name to fit with the current convention in the Tegra
header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This switches Ventana over to use FDT for run-time config instead of
CONFIG options.
At present Ventana does not have its own device tree file - it just uses
the Seaboard one.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This switches Seaboard over to use FDT for run-time config instead of
CONFIG options. USB is the only user at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Seaboard has a top port which is USB host or device, and a side port which
is host only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
All Tegra2 boards should include tegra2-common. This adds the required
USB config to that file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds basic USB support for port 0. The other port is not supported
yet.
Tegra2 (SeaBoard) # usb start
(Re)start USB...
USB: Register 10011 NbrPorts 1
USB EHCI 1.00
scanning bus for devices... 5 USB Device(s) found
scanning bus for storage devices... 1 Storage Device(s) found
Tegra2 (SeaBoard) # ext2load usb 0:3 10000000 /boot/vmlinuz
Loading file "/boot/vmlinuz" from usb device 0:3 (ROOT-A)
2932976 bytes read
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When using CONFIG_OF_CONTROL, add a check that we have a valid FDT
and panic() if not. This must be done after the console is ready.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
CONFIG_OF_CONTROL requires a valid device tree. However, we cannot call
panic() before the console is set up since the message does not appear,
and we get a silent failure.
Remove the panic from fdtdec_check_fdt() and provide a new function to
prepare the fdt for use. This will be called after the console is ready.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.
Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:
aliases {
/* This defines the order of our USB ports */
usb0 = "/usb@0xc5008000";
usb1 = "/usb@0xc5000000";
};
drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning
field in the EHCI controller on reset.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We set up two USB ports, one of which can be host or device.
For some reason the kernel version does enable both ports.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds clock references to the USB part of the device tree for U-Boot,
and marks USB1 as supporting legacy mode (which we disable in the driver).
The USB timing information may vary between boards sometimes, but for
now we hard-code it in C. This is because all current T2x boards use
the same values, we will deal with T3x later and we first need to agree
on the format for this timing information in the fdt and may in fact
decide that it has no place there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the definition of the oscillator clock frequency and the 32KHz clock.
The latter is provided by a PMIC on I2C which we don't actually use at
present, but we expect this definition to be used in the kernel and want
to keep our .dts the same.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds a basic binding for the oscillator and peripheral clocks. The
second cell is the clock number, defined as the bit number within the clock
enable register if the peripheral clock.
This uses the RFC clock bindings from Grant Likely so may change later:
https://lkml.org/lkml/2011/12/12/498
It is taken from Stephen Warren's patch here:
http://patchwork.ozlabs.org/patch/141359/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds a property to indicate a port which can switch between host and device
mode.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a directory to hold device tree binding files, to permit easy review
of this material in U-Boot patches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
config.mk is updated to provide this file to boards through the
built-in mechanism:
/include/ ARCH_CPU_DTS
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds some support into fdtdec for reading GPIO definitions from
the fdt. We permit up to FDT_GPIO_MAX GPIOs in the system. Each GPIO
is of the form:
gpio-function-name = <phandle gpio_num flags>;
where:
phandle is a pointer to the GPIO node
gpio_num is the number of the GPIO (0 to 223)
flags is a flag, as follows:
bit meaning
0 0=polarity normal, 1=active low (inverted)
An example is:
enable-propounder-gpios = <&gpio 43 0>;
which means that GPIO 43 is used to enable the propounder (setting the
GPIO high), or that you can detect that the propounder is enabled by
checking if the GPIO is high (the fdt does not indicate input/output).
Two main functions are provided:
fdtdec_decode_gpio() reads a GPIO property from an fdt node and decodes it
into a structure.
fdtdec_setup_gpio() sets up the GPIO by calling gpio_request for you.
Both functions can cope with the property being missing, which is taken to
mean that that GPIO function is not available or is not needed.
[For reference, from Stephen Warren <swarren@nvidia.com>. It may be that
we add this extra complexity later if needed:
The correct way to parse such a GPIO property in general is:
* Read the first cell.
* Find the node referenced by the phandle (the controller).
* Ensure property gpio-controller is present in the controller node.
* Read property #gpio-cells from the controller node.
* Extract #gpio-cells from the original property.
* Keep processing more cells from the original property; there may be
multiple GPIOs listed.
According to the binding documentation in the Linux kernel, Samsung
Exynos4 doesn't use this format, and while all other chips do have a
flags cell, about 50% of the controllers indicate the cell is unused.
]
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a function to look up a property which is a phandle in a node, and
another to read a fixed-length integer array from an fdt property.
Also add a function to read boolean properties, although there is no
actual boolean type in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This fixes five trivial issues in fdtdec.c:
1. fdtdec_get_is_enabled() doesn't really need a default value
2. The fdt must be word-aligned, since otherwise it will fail on ARM
3. The compat_names[] array is missing its first element. This is needed
only because the first fdt_compat_id is defined to be invalid.
4. Added a header prototype for fdtdec_next_compatible()
5. Change fdtdec_next_alias() to only increment its 'upto' parameter
on success, to make the display error messages in the caller easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The fdtdec_find_aliases_for_id() function is complicated enough that
it really should have some tests. This does not necessarily need to be
committed to U-Boot, but it might be useful.
(note there are a few minor inconsistencies with this patch which will be
cleaned up when the USB series is applied)
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren pointed out that we should use nodes whether or not they
have an alias in the /aliases section. The aliases section specifies the
order so far as it can, but is not essential. Operating without alisses
is useful when the enumerated order of nodes does not matter (admittedly
rare in U-Boot).
This is considerably more complex, and it is important to keep this
complexity out of driver code. This patch creates a function
fdtdec_find_aliases() which returns an ordered list of node offsets
for a particular compatible ID, taking account of alias nodes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
load using a constant in tegra2_start. Change it to use a load
thru another reg using mov sp, %0 : : "r"(CONST).
Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Ensure that transmit and receive buffers are cache-line aligned.
Invalidate cache for each packet as received, update receive buffer
descriptors one cache line at a time, flush cache before transmitting.
Original patch by Marek:
http://lists.denx.de/pipermail/u-boot/2012-February/117695.html
Signed-off-by: Eric Nelson <eric.nelson at boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This will prevent the need for architectures whose DMA alignment
is greater than 32 to have bounce buffers.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This utilizes the newly introduced bounce buffers in the MMC layer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
This implements generic bounce buffer at the end of MMC command submission
chain. Therefore if unaligned data are passed, they are copied. This stuff
should be pushed down into the MMC subsystem to squash all places generating
these unaligned data.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Building for vpac270_ond_256 configuration fails:
arch/arm/lib/libarm.o: In function `icache_disable':
/home/ag/git/u-boot/arch/arm/lib/cache-cp15.c:156: multiple
definition of `icache_disable'
board/vpac270/libvpac270.o:/home/ag/git/u-boot/board/vpac270/onenand.c:65:
first defined here
arch/arm/lib/libarm.o: In function `dcache_disable':
/home/ag/git/u-boot/arch/arm/lib/cache-cp15.c:188: multiple
definition of `dcache_disable'
board/vpac270/libvpac270.o:/home/ag/git/u-boot/board/vpac270/onenand.c:66:
first defined here
make[1]: *** [/home/ag/git/u-boot/spl/u-boot-spl] Error 1
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
