Import cvmx-sata-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-rst-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pow-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pko-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pki-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pip-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pepx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pemx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pcsx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pciercx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-pcieepx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-npi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-mio-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-l2c-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-ipd-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-gserx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-gmxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-fpa-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-dtx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-dpi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-dbg-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-ciu-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-bgxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-asxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import cvmx-agl-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import misc cvmx-helper header files from 2013 U-Boot. They will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This will be used by the upcoming Serdes and driver code ported from
the original 2013 U-Boot code to mainline.
Signed-off-by: Stefan Roese <sr@denx.de>
Add the MMC DT node to the Octeon EBB7304 DT file including the
regulator node for the MMC power supply.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add the MMC DT node to the Octeon CN73xx dtsi file.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Until now, the Octeontx MMC driver did only support the ARM Octeon
TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform
to this driver. Here a short summary of the changes:
- Enable driver compilation for MIPS Octeon, including the MMC related
header file
- Reorder header inclusion
- Switch to using the clk framework to get the input clock
- Remove some functions for MIPS Octeon, as some registers don't
exist here
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
from bootstrap register must be ignored, and always be assumed as DDR1.
This patch fixes the displayed DDR type of mt7628.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
from bootstrap register must be ignored, and always be assumed as DDR1.
This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed
with a wrong ddr_type in MT7688KN.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Make sure to reset the switch core at probe time.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add support for stack protector for UBOOT, SPL, and TPL
as well as new pytest for stackprotector
Signed-off-by: Joel Peshkin <joel.peshkin@broadcom.com>
Adjust UEFI build flags.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The current usage of the variable CFLAGS_NON_EFI on the x86 architecture
deviates from other architectures.
Variable CFLAGS_NON_EFI is the list of compiler flags to be removed when
building UEFI applications. It is not a list of flags to be added anywhere.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
So far U-Boot was hard coding a (surely sufficient) memory size of 512
MB, even though all machines out there have at least 4GB of DRAM.
Since U-Boot uses its memory knowledge to populate the EFI memory map,
we are missing out here, at best losing everything beyond 4GB on Midway
boxes (which typically come with 8GB of DRAM).
Since the management processor populated the DT memory node already with
the detected DRAM size and configuration, we use that to populate
U-Boot's memory bank information, which is the base for the UEFI memory
map.
This finally allows us to get rid of the NR_DRAM_BANKS=0 hack, that we
had in place to avoid U-Boot messing up the DT memory node before
loading the kernel.
Also, to cover the whole of memory, we need to enable PHYS_64BIT.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
To squash that nasty warning message and make better use of the newly
gained OF_CONTROL feature, let's convert the calxedagmac driver to the
"new" driver model.
The conversion is pretty straight forward, mostly just adjusting the
use of the involved data structures.
The only actual change is the required split of the receive routine into
a receive and free_pkt part.
Also this allows us to get rid of the hardcoded platform information and
explicit init calls.
This also uses the opportunity to wrap the code decoding the MMIO
register base address, to make it safe for using PHYS_64BIT later.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
All Calxeda machines are actually a poster book example of device tree
usage: the DT is loaded from flash by the management processor into
DRAM, the memory node is populated with the detected DRAM size and this
DT is then handed over to the kernel.
So it's a shame that U-Boot didn't participate in this chain, but
fortunately this is easy to fix:
Define CONFIG_OF_CONTROL and CONFIG_OF_BOARD, and provide a trivial
function to tell U-Boot about the (fixed) location of the DTB in DRAM.
Then enable DM_SERIAL, to let the PL011 driver pick up the UART platform
data from the DT. Also define AHCI, to bring this driver into the driver
model world as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
use 'select' to enable IRQ as it does not have architecture
specific dependency.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".
And as the following statement, we here clear the whole Pending tables
instead of the first 1KB.
"An LPI Pending table that contains only zeros, including in the first 1KB,
indicates that there are no pending LPIs.
The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
if the first 1KB of the LPI Pending table and the rest of the table contain
only zeros, this must indicate that there are no pending LPIs."
And there isn't any pending LPI under U-Boot, so it's unnecessary to
load the contents of the Pending table during the enablement, then set
the GICR_PENDBASER.PTZ flag.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # NXP LS1028A
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable PCIe by default in u-boot, this should eventually be made dynamic
in the runtime board config depending on the MCU configuration.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The sync of the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
ODROID-C2. The PHY seems to need proper reset timing to be functional
in U-Boot and Linux afterwards. Readd the old PHY reset bindings for
dwmac until we support the new bindings in the PHY node.
Fixes: dd5f2351e9 ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Merge tag 'u-boot-atmel-2021.07-b' of https://source.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel features for 2021.07 cycle:
This small feature set include support for 5th PIO bank on pio4 pinctrl
driver and a fix for the SPL on sama5d3.
This reverts commit 38d6b7ebda.
struct global_data contains a pointer to the bd_info structure. This
pointer was populated spl_set_bd() to a pre-allocated bd_info in the
".data" section. The referenced commit replaced this mechanism to one
that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
which very few boards do.
The result is that (struct global_data)->bd is NULL in SPL on most
platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
access (struct global_data)->bd and set the "/memory" node in the
devicetree. The result is that the "/memory" node contains garbage
values, causing linux to panic() as it sets up the page table.
Instead of trying to fix the mess, potentially causing other issues,
revert to the code that worked, while this change is reworked.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
in the early SPL boot stage whenever there is a call to udelay,
dm_timer_init fails to find the pit timer whenever it traverses
the device tree, if this property is not present
Signed-off-by: Manuel Reis <mluis.reis@gmail.com>
CC: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
This is a patchset which makes away with the .bind() controller indexing
workaround which was broken since before v2021.04, and then adds PHY
support and MX8M support on top of that. Better add it into the release
early to get as much testing as possible done, because this really does
a lot of changes to the ehci-mx6 driver.
