Commit graph

84699 commits

Author SHA1 Message Date
Yu Chien Peter Lin
da24626d14 driver: cache-v5l2: Fix type casting warning on RV32
This patch fixes following warning for the riscv32 toolchain.

drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  122 |         regs = (struct l2cache *)dev_read_addr(dev);
      |                ^

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
f29834d150 configs: ae350: Display CPU and board info for AE350 platforms
Display information about CPU and board during start up.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
d002b2a187 configs: ae350: Increase maximum retry count for AE350 platforms
Loading an image via TFTP is often interrupted when retrying more than
10 times, increase the number of retries so that it does not simply stop
the transfer.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
487c211ef6 configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit:
ca06444aac

Turing on does not significantly increase the size of u-boot-spl.bin,
so we enable it by default to improve performance.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
600a708c05 riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
This patch refines L1 cache enable/disable and v5l2-cache enable
functions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
c1b8819680 riscv: ae350: dts: Update L2 cache compatible string
Update the compatible string of L2 cache.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
d8a146d19b riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.

[0] bd7ef41398

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
51415fa634 driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform
The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
e74e21ceb3 board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
The L2-cache is not enabled currently, the enbale_caches() will call
the v5l2_enable() callback to enable it in SPL.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Leo Yu-Chi Liang
55ca747f66 riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
daf1312b07 riscv: global_data.h: Correct the comment for PLICSW
PLIC is used for external interrupt, while PLICSW is an Andes-specific
design for software interrupt.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Tom Rini
faac9dee8e Prepare v2023.04-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-13 18:39:15 -05:00
Sumit Garg
b97487db4e clocks: qcs404: Add support for I2C clocks
Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-13 10:01:52 -05:00
Tom Rini
d7bcd6ee40 Merge tag 'i2c-updates-for-v2023.04' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2023.04

- add new i2c driver ast2600 from Ryan Chen

- i2c-cdns: make read fifo-depth configurable through device tree
  from Pei Yue Ho

- mxc i2c driver: print base address in hex, not in decimal
  from Fabio
2023-02-13 09:57:35 -05:00
Tom Rini
be9399b399 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Support for 2 new Armada 385 boards (Tony)
- mvebu: Minor misc board enhancements (Tony)
- kirkwood: Serial driver fixes (Kconfig & dtsi) (Tony)
- cmd: return code when tlv_eeprom incorrectly called (Heinrich)
2023-02-13 09:39:15 -05:00
Tony Dinh
dd15284b74 arm: kirkwood: Enable uart0 dm-pre-reloc for Pogoplug V4 board
When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is
required for this board to boot over UART with kwboot. Enable this in
kirkwood-pogoplug-series-4-u-boot.dtsi.

Added by Stefan while applying:
Please note that it's not fully understood, why this property really
is needed. Here a link to the discussion about this:

https://lore.kernel.org/r/20230201080210.ypz4nrj4y2igwxz3@pali/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13 10:15:04 +01:00
Tony Dinh
b21f87a5a5 arm: mvebu: Add support for Synology DS116 (Armada 385)
Synology DS116 is a NAS based on Marvell Armada 385 SoC.

Board Specification:

- Marvel MV88F6820 Dual Core at 1.8GHz
- 1 GiB DDR3 RAM
- 8MB Macronix mx25l6405d SPI flash
- I2C
- 2x USB 3.0
- 1x GBE LAN port (PHY: Marvell 88E1510)
- 1x SATA (6 Gbps)
- 3x LED
- PIC16F1829 (connected to uart1)
- GPIO fan
- serial console

Note that this patch depends on the add-support for Thecus N2350 patch:
https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2023-02-13 10:14:50 +01:00
Tony Dinh
384e2d396c arm: mvebu: Power up 2nd SATA port for Thecus N2350
Currently, only the 1st SATA port is powered up (by GPIO1 12).
Add GPIO1 13 in board initialization to power up the 2nd SATA port.

Note that this patch depends on the initial add-support patch:
https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13 10:14:50 +01:00
Tony Dinh
0ca42c18a8 arm: kirkwood: sheevaplug: reduce u-boot image size
Sheevaplug board has 512K CONFIG_BOARD_SIZE_LIMIT. Recently, DM_SERIAL has
pushed the image size a few hundred bytes over that limit. So explicitly
deselect some configs that are unrelated to this board
(and gain back a bit over 2K).

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2023-02-13 10:14:50 +01:00
Tony Dinh
3fdd09f90f arm: mvebu: Add support for Thecus N2350 (Armada 385) board
Thecus N2350 is a NAS based on Marvell Armada 385 SoC.

Specification:

- Processor: Marvel MV88F6820 Dual Core at 1GHz
- 1 GiB DDR4 RAM
- 4MB Macronix mx25l3205d SPI flash
- 512MB Hynix H27U4G8F2DTR-BC NAND flash
- I2C
- 2x USB 3.0
- 1x GBE LAN port (PHY: Marvell 88E1510)
- 2x SATA (hot swap slots)
- 3x buttons
- 10x LEDS
- serial console

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13 10:14:50 +01:00
Tony Dinh
5c73428f4a arm: kirkwood: Use CONFIG_SYS_NS16550 with DM_SERIAL for Kirkwood boards
CONFIG_SYS_NS16550 is required when DM_SERIAL is enabled for
Kirkwood boards.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13 10:14:50 +01:00
Heinrich Schuchardt
93a80c1515 cmd: return code when tlv_eeprom incorrectly called
A command called with incorrect parameters should set $? to 1 (false).
Instead of calling cmd_usage(cmdtp) and then returning 0 just return
CMD_RET_FAILURE.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13 10:14:50 +01:00
Pei Yue Ho
f536fda99f i2c: i2c-cdns.c: Update driver to read fifo-depth from device tree
Enable driver to fetch the optional parameter (fifo-depth) from device
tree. If the parameter is not found in the device tree, it will use
the default value declared in the driver.

Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:58:27 +01:00
Pei Yue Ho
8511a7fc85 dt-bindings: i2c: i2c-cdns.txt: Add description for an optional parameter, fifo-depth
Add description for fifo-depth parameter that can be used
in the device tree.

Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:58:15 +01:00
Ryan Chen
87f5b5d683 arm: aspeed: dtsi: add reg for i2c
The i2c driver have global register that i2c bus use
ofnode_get_parent to get parent register address.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:57:58 +01:00
Ryan Chen
4088f5fce8 i2c:aspeed:support ast2600 i2c new register mode driver
Add i2c new register mode driver to support AST2600 i2c
new register mode. AST2600 i2c controller have legacy and
new register mode. The new register mode have global register
support 4 base clock for scl clock selection, and new clock
divider mode.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:57:49 +01:00
Fabio Estevam
371be1e012 i2c: mxc_i2c: Use hex notation for the base address
Printing the I2C controller base address in decimal notation
is not helpful.

Change it to hex notation, which is the standard format found
in the Reference Manual and devicetree.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:57:30 +01:00
Tom Rini
06fe737d1d minor changes to fdt command and binman
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Merge tag 'dm-pull-12feb23' of https://source.denx.de/u-boot/custodians/u-boot-dm

minor changes to fdt command and binman
2023-02-12 20:11:22 -05:00
Andre Przywara
4ee85df9ce cmd: fdt: allow standalone "fdt move"
At the moment every subcommand of "fdt", except "addr" itself, requires
the DT address to be set first. We explicitly check for that before even
comparing against the subcommands' string.
This early bailout also affects the "move" subcommand, even though that
does not require or rely on a previous call to "fdt addr". In fact it
even sets the FDT address to the target of the move command, so is a
perfect beginning for a sequence of fdt commands.

Move the check for a previously set FDT address to after we handle the
"move" command also, so we don't need a dummy call to "fdt addr" first,
before being able to move the devicetree.

This skips one pointless "fdt addr" call in scripts which aim to alter
the control DT, but need to copy it to a safe location first (for
instance to $fdt_addr_r).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-12 17:33:51 -07:00
Andre Przywara
6459734619 cmd: fdt: move: Use map_sysmem to convert pointers
The "fdt move" subcommand was using the provided DTB addresses directly,
without trying to "map" them into U-Boot's address space. This happened
to work since on the vast majority of "real" platforms there is a simple
1:1 mapping of VA to PAs, so either value works fine.

However this is not true on the sandbox, so the "fdt move" command fails
there miserably:
=> fdt addr $fdtcontroladdr
=> cp.l $fdtcontroladdr $fdt_addr_r 40  # simple memcpy works
=> fdt move $fdtcontroladdr $fdt_addr_r
Segmentation fault

Use the proper "map_sysmem" call to convert PAs to VAs, to make this
more robust in general and to enable operation in the sandbox.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-12 17:33:51 -07:00
Simon Glass
193d3dbd45 binman: Show the image name for the top-level section
At present we show 'main section' as the top-level section name. It may
be more helpful to show the actual image name. This is tricky because
Image is a parent class of Entry_section, so there is no distinction
between an image and a section.

Update it to show the image name.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-12 17:33:51 -07:00
Jade Lovelace
a5e490f14e socfpga: fix the serial console on DE1-SoC
Previously, the TX LED would flash but nothing would appear on the
serial port, and the board would appear dead with a build of the
socfpga_cyclone5_defconfig. I have verified that adding the frequency to
the uart will fix the serial console on my board.

Thanks to @ehoffman on the Rocketboards forum:
https://forum.rocketboards.org/t/cyclonev-programming-fpga-from-u-boot/2230/30

Signed-off-by: Jade Lovelace <lists@jade.fyi>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-12 15:47:19 -05:00
Tom Rini
9345f165eb Clock changes for 2023.04-rc1
This contains various fixes and small features. I've included a reset patch as
 well since it was in the same series as a clock patch.
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Merge tag 'clk-2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-clk

Clock changes for 2023.04-rc1

This contains various fixes and small features. I've included a reset patch as
well since it was in the same series as a clock patch.
2023-02-12 15:25:32 -05:00
Tom Rini
386e77cda8 Merge branch 'for-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
- A fix for a long standing bug that has been exposed by commit
  50128aeb0f ("cyclic: get rid of cyclic_init()") preventing 8xx boards
  from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.
2023-02-12 15:25:09 -05:00
Samuel Holland
5a675abfe7 reset: Allow reset_get_by_name() with NULL name
This allows devm_reset_control_get(dev, NULL) to work and get the first
reset control, which is common in code ported from Linux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
2023-02-12 13:44:20 -05:00
Samuel Holland
2050f824e1 clk: Allow clk_get_by_name() with NULL name
This allows devm_clock_get(dev, NULL) to work and get the first clock,
which is common in code ported from Linux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
2023-02-12 13:44:20 -05:00
Patrick Delaunay
c40251c120 cmd: clk: probe the clock before dump them
The clock UCLASS need to be probed to allow availability of the
private data (struct clk *), get in show_clks() with dev_get_clk_ptr()
before use them.

Without this patch the clock dump can cause crash because all the
private data are not available before calling the API clk_get_rate().

It is the case for the SCMI clocks, priv->channel is needed for
scmi_clk_get_rate() and it is initialized only in scmi_clk_probe().
This issue causes a crash for "clk dump" command on STM32MP135F-DK board
for SCMI clock not yet probed.

Fixes: 1a725e2290 ("clk: fix clock tree dump to properly dump out every registered clock")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221213145708.v2.1.Ia0bc6b272f1e2e3f37873c61d79138c2663c4055@changeid
2023-02-12 13:37:56 -05:00
Dario Binacchi
4a18d23039 clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
[backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b]

According to the "Clock Root" table of the reference manual (document
IMX8MNRM Rev 2, 07/2022):

     Clock Root         offset     Source Select (CCM_TARGET_ROOTn[MUX])
        ...              ...                    ...
 ENET_PHY_REF_CLK_ROOT  0xAA80            000 - 24M_REF_CLK
                                          001 - SYSTEM_PLL2_DIV20
                                          010 - SYSTEM_PLL2_DIV8
                                          011 - SYSTEM_PLL2_DIV5
                                          100 - SYSTEM_PLL2_DIV2
                                          101 - AUDIO_PLL1_CLK
                                          110 - VIDEO_PLL_CLK
                                          111 - AUDIO_PLL2_CLK
        ...              ...                    ...

while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
source select bits 101b.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-4-dario.binacchi@amarulasolutions.com
2023-02-12 12:39:46 -05:00
Dario Binacchi
e02bf587d3 clk: imx: rename video_pll1 to video_pll
[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6]

Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.

No functional changes intended.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
2023-02-12 12:39:46 -05:00
Dario Binacchi
d0cc6a6ca1 clk: imx8mn: rename vpu_pll to m7_alt_pll
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df]

The IMX8MN platform does not have any video processing unit (VPU), and
indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there
is no occurrence of its pll. From an analysis of the code and the RM
itself, I think vpu pll is used instead of m7 alternate pll, probably
for copy and paste of code taken from modules of similar architectures.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
2023-02-12 12:39:46 -05:00
Jim Liu
07f5399f04 clk: nuvoton: fix bug for calculate pll clock
Fix bug for npcm7xx bmc calculate pll clock.
PLLCON1 need to divide by 2.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
2023-02-12 12:39:46 -05:00
Sjoerd Simons
0d91c88230 lmb: Treat a region which is a subset as equal
In various cases logical memory blocks are coalesced; As a result doing
a strict check whether memory blocks are the same doesn't necessarily
work as a previous addition of a given block might have been merged into
a bigger block.

Fix this by considering a block is already registered if it's a pure
subset of one of the existing blocks.

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
2023-02-12 11:54:18 -05:00
Tom Rini
78d1c3949a Merge branch '2023-02-10-update-trace-feature-to-work-with-trace-cmd'
To quote the author:
Since U-Boot's tracing feature was originally written, quite a few changes
have taken place in this domain. The original text format used by tracing
is still emitted by Linux, but a new trace-cmd tool has invented a binary
format which is now used by new tools, such as kernelshark.

With recent distributions and the move to Python 3, the old pybootchart
tool does not build or run. Unfortunately there is no 1:1 replacement for
the features that were provided by pybootchart, or at least it is not
obvious. Still, it makes sense to keep with the times.

This series updates proftool to use the new binary format, adding support
for function and funcgraph tracing, so that U-Boot's trace records can be
examined by trace-cmd and kernelshark.

This series also adds support for a flamegraph, which provides a visual
way to see which functions are called a lot, as well as which ones consume
the most time.

Some minor updates to the trace implementation within U-Boot are included,
to provide a little more information and to fix a few problems.

No unit tests are provided by proftool, but a functional test ensures that
sandbox can emit traces which can be processed by proftool, then parsed by
trace-cmd and that the timing of the various formats looks consistent.
2023-02-12 10:56:54 -05:00
Tom Rini
16bf3b6f8f CI, Docker: Update to Jammy 2023016 tag
Move to the latest tag for "Jammy" and rebuild the containers.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-11 12:22:35 -05:00
Simon Glass
e46b72436c trace: Update documentation
Revamp the documentation for the new features, including a description of
the new features and documentation for the trace command.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-11 12:22:35 -05:00
Simon Glass
9cea4797ae trace: Add a test
Add a test which runs sandbox, collects a trace and makes sure it can
be processed by trace-cmd. This should ensure that this feature continues
to work as U-Boot and trace-cmd evolve.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-11 12:22:35 -05:00
Simon Glass
71d3e7949c Docker: Support trace-cmd
Build trace-cmd as part of the docker image, so that trace tests can be
used. Unfortunately the version provided by distributions is a little old
and has bugs. It also does not support specifying the time base for the
trace, which is required to convert microseconds to nanaseconds.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-11 12:22:35 -05:00
Simon Glass
97f3024d16 trace: Provide a flamegraph that uses timing
Add a second variant of the flame graph that shows records in terms of the
number of microseconds used by each call stack. This is a useful way of
seeing where time is going within the execution of U-Boot.

This requires a call stack that records the start time of each function,
as well as a way of subtracting all time consumed by child functions, so
that this time is not counted twice by the flamegraph. The time values in
the output are just for the function itself, not for its children.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-11 12:22:35 -05:00
Simon Glass
47b89d61f2 trace: Support output of a flamegraph
It is useful to see how many times each function is called, particularly
in the context of its callers. A flamegraph is a way of showing this.

Support output in this format which can be used by the flamegraph.pl
script, to generate an SVG image for browsing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-11 12:22:35 -05:00
Simon Glass
b54d8cf0b5 trace: Support output of funcgraph records
Add support for writing ftrace records in the 'funcgraph' format, which
shows function entry and exit points as well as the time taken by each
function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-11 12:22:35 -05:00