Commit graph

21 commits

Author SHA1 Message Date
Kumar Gala
355f4f85e9 ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation
Now that we track which TLB CAM entries are used we can allocate
entries on the fly.  Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Kumar Gala
94e9411b9d ppc/85xx: Add tracking of TLB CAM usage
We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code.  For example the SPD
DDR code today hard codes which TLB entries it uses.  We can now make
that pick entries that are free.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Kumar Gala
cdbdbe65f5 ppc/85xx: Fix how we determine the number of CAM entries
We were incorrectly use the max CAM size as the number of entries in
the array for setting up the addrmap.  We should be using the NENTRY
field which is the low 12-bits of TLB1CFG.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-13 09:11:01 -06:00
Mingkai Hu
7da53351d8 ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
b2eec281a8 ppc/85xx: Move code around to prep for NAND_SPL
If we move some of the functions in tlb.c around we need less
ifdefs.  The first stage loader just needs invalidate_tlb and
init_tlbs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
206af3527c ppc/85xx: Repack tlb_table to save space
We can pack the initial tlb_table in MAS register format and use
write_tlb to set things up.  This savings can be helpful for NAND
style first stage boot loaders.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
d30f904353 ppc/85xx: Introduce low level write_tlb function
Factor out the code we use to actually write a tlb entry.

set_tlb is a logical view of the TLB while write_tlb is a low level
matching the MAS registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:08 -05:00
Scott Wood
dcc87dd58d ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.
Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:08 -05:00
Kumar Gala
c2287af155 ppc/85xx: Add a simple function to search the TLB
Allow us to search the TLB array based on an address.  This is useful
if we want to change an entry but dont know where it happens to be
located.

For example, the boot page mapping we use on MP or the flash TLB that
we change the WIMGE settings for after we've relocated.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:05 -05:00
Wolfgang Denk
963f2f6117 Prepare 2009.08-rc3
Update CHANGELOG, minor Coding Style cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-08-22 23:27:26 +02:00
Kumar Gala
e393e2e9bc 85xx: Fix addrmap to include memory
When we init the addrmap based on the TLB we will not end up getting
the TLB that covers memory if we are using SPD.  The reason is we
haven't relocated at the point that we setup the memory TLB and thus it
will not get setup in the addrmap.

Instead we can just walk over the TLB array after we've relocated and
see all the TLBs that have been set and use that information to populate
the initial addrmap.  By doing this we insure that we get the TLB
entries that cover memory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-14 17:42:05 -05:00
Kumar Gala
d4b130dc80 85xx: Use print_size to report amount of memory not mapped by TLBs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 09:15:48 -05:00
Fredrik Arnerup
90d13b8ac3 85xx: bugfix for reading maximum TLB size on mpc85xx
The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits.
This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum
(256 MB)
which made u-boot hang in board_init_f() when trying to create a new stack
in RAM.
I have an mpc8540 with one 1GB dimm.

Signed-off-by: Fredrik Arnerup <fredrik.arnerup@edgeware.tv>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-09 22:58:18 +02:00
Kumar Gala
f8523cb081 85xx: Fix how we map DDR memory
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:51 -06:00
Haiying Wang
950264317e Change DDR tlb start entry to CONFIG param for 85xx
So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-13 16:47:07 -06:00
Kumar Gala
ecf5b98c7a 85xx: Add support to populate addr map based on TLB settings
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-19 18:20:08 -06:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Kumar Gala
6fb1b73468 FSL DDR: Add e500 TLB helper for DDR code
Provide a helper function that board code can call to map TLBs when
setting up DDR.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:48 -05:00
Wolfgang Denk
865f0f9754 Coding Style Cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-23 14:31:17 +01:00
Kumar Gala
7dc358bb0d 85xx: Get ride of old TLB setup code
Now that all boards have been converted, remove old config code and the
config option for the new style.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:19:18 -06:00
Kumar Gala
44a23cfd63 85xx: Introduce new tlb API
Add a set of functions to manipulate TLB entries:
 * set_tlb() - write a tlb entry
 * invalidate_tlb() - invalidate a tlb array
 * disable_tlb() - disable a variable size tlb entry
 * init_tlbs() - setup initial tlbs based on static table

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:04:07 -06:00