4 commits

Author	SHA1	Message	Date
Matt Ranostay	28ba10074b	phy: ti: j721e-wiz: add j784s4-wiz-10g module support ... Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Signed-off-by: Matt Ranostay <mranostay@ti.com>	2022-10-18 09:48:22 -04:00
Matt Ranostay	ea3e163f21	phy: ti: j721e-wiz: use OF data for device specific data ... Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u Cc: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com>	2022-07-25 09:38:47 -04:00
Aswath Govindraju	ff0becea71	phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE ... Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>	2022-02-08 11:00:03 -05:00
Jean-Jacques Hiblot	1a83f9931e	phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC ... Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com	2021-07-27 10:57:12 +05:30