29 commits

Author	SHA1	Message	Date
stroese	afcc4a7404	Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.	2003-04-04 16:52:57 +00:00
wdenk	ac6dbb85b7	Make compile clean, fix the usual small problems.	2003-03-26 11:42:53 +00:00
stroese	2a46cabd77	esd PCI405 updated.	2003-03-26 10:36:12 +00:00
stroese	d69b100e70	esd PCI405 updated.	2003-03-25 14:41:35 +00:00
stroese	6f4474e87b	CPCI4052 update (support for revision 3).	2003-03-20 15:31:19 +00:00
stroese	ad10dd9aaf	Add "pcidelay" environment variable (in ms, enabled via CONFIG_PCI_BOOTDELAY).	2003-02-14 11:21:23 +00:00
wdenk	37bd321e99	Initial revision	2002-11-03 11:21:28 +00:00
wdenk	fe8c2806cd	Initial revision	2002-11-03 00:38:21 +00:00
wdenk	c609719b8d	Initial revision	2002-11-03 00:24:07 +00:00
wdenk	458ded34b6	Initial revision	2002-09-20 10:59:08 +00:00
wdenk	ab255f26f9	Initial revision	2002-09-18 09:04:55 +00:00
wdenk	153d511e36	Initial revision	2002-08-30 11:07:04 +00:00
wdenk	16f217049a	Initial revision	2002-08-26 21:58:50 +00:00
wdenk	affae2bff8	Initial revision	2002-08-17 09:36:01 +00:00
wdenk	2f54faae47	Initial revision	2002-08-14 10:07:21 +00:00
wdenk	935ecca1c3	Initial revision	2002-08-06 20:46:37 +00:00
wdenk	efee170991	Initial revision	2002-07-20 20:14:13 +00:00
wdenk	befe61a190	Initial revision	2002-07-18 16:07:27 +00:00
wdenk	3cae4c9f61	Initial revision	2002-07-07 16:05:51 +00:00
wdenk	c7b3f07f4b	Initial revision	2002-06-07 13:44:57 +00:00
wdenk	0312e6a7f3	Initial revision	2002-05-15 20:47:18 +00:00
wdenk	e85390dc1d	Initial revision	2002-04-01 14:29:03 +00:00
wdenk	67fc21f34e	Initial revision	2002-03-02 09:46:26 +00:00
wdenk	b92ab0d727	Initial revision	2001-12-28 14:40:42 +00:00
wdenk	12e4407c6a	Initial revision	2001-11-26 22:06:16 +00:00
wdenk	89ab65e00c	Initial revision	2001-10-15 21:41:43 +00:00
wdenk	349e1442f3	Initial revision	2001-10-07 12:15:54 +00:00
wdenk	2dab301caa	Initial revision	2001-08-05 15:35:05 +00:00
wdenk	a475b5e2a0	Initial revision	2001-07-19 16:11:32 +00:00