Starts to use new way how eeproms should be referenced.
Reference is done via nvmem alias nodes. When this new way is specified
code itself read the eeprom and decode xilinx legacy format and fill struct
xilinx_board_description. Then based on information present there board_*
variables are setup.
If variables are saved and content can't be changed information is just
shown on console.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG to enable/disable updating
variables with run time information.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Removes duplicated definition of PAYLOAD_ARG_CNT and define it in the
firmware driver. Additionally fixes payload buffer declarations without
macro usage
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Find and use the lowest memory for Versal to make sure that we keep u-boot
as low as possible and never use memory above u-boot's maximum VA mapping.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Versal loadpdi command is used for loading secure & non-secure
pdi images.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.
Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.
This requires quite a few header-file additions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.
Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Create special function for reading bootmode on Versal and ZynqMP.
Zynq is using specific function (without mask) already.
Future patches will be calling this function from different location too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Currently "script_offset_f" env variable is hardcoded, this variable
specifies from which offset of the flash boot.scr should be read/write.
As flashes are of different sizes having a fixed offset makes it
difficult to load other images into the flash which may overwrite the
boot script or cannot utilize the full memory. This current fix
creates a new config "CONFIG_BOOT_SCRIPT_OFFSET" which holds the
offset address, overwrites the "script_offset_f" variable.
Also removed existing variable with default values, as the default
values are held by CONFIG_BOOT_SCRIPT_OFFSET
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Emmc boot devcie is mounted to sdhci@f1050000 controller on versal, while
in emmc boot mode, boot tragets are set to mmc0. So removed mmc0 and using
the dev seq number from the sdhci@f1050000 controller.
Dev seq number is setup based on DT aliases that's why needs to be setup at
run time.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
A number of board function belong in init.h with the others. Move them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move the exisiting function of getting board dtb from versal to a common
Xilinx folder.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds new dfu usb distro boot command to look for bootscript
from dfu-util and runs it.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
This patch adds new jtag distro boot command to look for bootscript file
in DDR and execute it first incase of jtag bootmode.
This patch also updates scriptaddr to 512MB as there is high of script
corruption incase of bigger kernel image.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Code reads DT and setup MMU table based on memory node. This will ensure
that only DT needs to be changed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is setting up the initrd_high to as high as possible by leaving
max stack size for u-boot so that bigger rootfs can also be loaded by
u-boot for booting kernel.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define board_late_init which performs bootmode detection
and prepares corresponding distro boot commaand sequence.
Also disable it for mini platforms because simply there is no need to have
it enabled.
But also disable it for virtual platform because Qemu is not modelling this
register space that's why travis testing would fail. This configuration
should be reverted when mainline Qemu is updated.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.
The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
