Commit graph

259 commits

Author SHA1 Message Date
Kumar Gala
39aaca1f66 ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms.  Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks.  We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:29 -05:00
Kumar Gala
3c2a67eec8 ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:29 -05:00
Kumar Gala
7e4259bba4 ppc/p4080: Add various p4080 related defines (and p4040)
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Kumar Gala
39a7e7fd53 ppc/p4080: CoreNet platfrom style secondary core release
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style.  Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Kumar Gala
a880cf3e0e ppc/p4080: CoreNet platfrom style CCSRBAR setting
On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-24 12:05:28 -05:00
Kumar Gala
25bacf7a2b ppc/85xx: Fix enabling of L2 cache
We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:27 -05:00
Vivek Mahajan
cb0ff65c61 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ
The code assumed names where just numbers and always prefixed 'mpc'.
However newer QorIQ don't follow the mpc naming scheme.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:27 -05:00
Mingkai Hu
234a89d911 ppc/85xx: add cpu init config file for boot from NAND
When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:26 -05:00
Mingkai Hu
098bcbae31 ppc/85xx: add ld script file for boot from NAND
The first stage 4K image uses a seperate ld script file to
generate 4K image. This patch moves it to the cpu/mpc85xx/*
to make it avaliable for 85xx platform.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:25 -05:00
Kumar Gala
15fba3279b ppc/85xx: Disable all async interrupt sources when we boot
We should make sure to clear MSR[ME, CE, DE] when we boot an OS image
since we have changed the exception vectors and the OSes vectors might
not be setup we should avoid async interrupts at all costs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
9f00409a9d ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL
By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
0456dbf347 ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL
Use write_tlb and don't use memset so we can use the same code for
cpu_init_early_f between NAND SPL and not.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Mingkai Hu
7da53351d8 ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
b2eec281a8 ppc/85xx: Move code around to prep for NAND_SPL
If we move some of the functions in tlb.c around we need less
ifdefs.  The first stage loader just needs invalidate_tlb and
init_tlbs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
206af3527c ppc/85xx: Repack tlb_table to save space
We can pack the initial tlb_table in MAS register format and use
write_tlb to set things up.  This savings can be helpful for NAND
style first stage boot loaders.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
d30f904353 ppc/85xx: Introduce low level write_tlb function
Factor out the code we use to actually write a tlb entry.

set_tlb is a logical view of the TLB while write_tlb is a low level
matching the MAS registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:08 -05:00
Scott Wood
3e3c9c157b ppc/85xx: Remove some bogus code from external interrupt handler.
Skipping the interrupted instruction will accomplish nothing other
than turning a spurious interrupt into a crash.

External interrupts are not machine checks, so don't count them as such.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:08 -05:00
Scott Wood
dcc87dd58d ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.
Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:08 -05:00
Scott Wood
1b72dbecca ppc/85xx: Don't enable interrupts before we're ready
We cannot handle any exceptions while running in AS1, as the exceptions
will transition back to AS0 without a valid mapping.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:07 -05:00
Kumar Gala
6c97a20d0b ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address
Some board ports place TEXT_BASE at a location that would cause the
RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link.  By default
we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't
explicitly set it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-09-09 21:04:47 -05:00
Kumar Gala
c348322ac7 ppc/85xx: Clean up do_reset
There is no reason to do a run time check for e500 v1 based cores to
determine if we have the GUTs RSTCR facility.  Only the first generation
of PQ3 parts (MPC8540/41/55/60) do not have it.  So checking to see if
we are e500 v2 would miss future parts (like e500mc).

Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 13:47:18 -05:00
Poonam Aggrwal
21170c80a8 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().
While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Poonam Aggrwal
f8027f6b47 ppc/85xx/86xx: Device tree fixup for number of cores
Fixing the number of cores in the device tree based on the actual number of
cores on the system.  With this same device tree image can be used for dual
core and single core members of otherwise exactly same SOC.

For example:
* P2020RDB and P2010RDB
* P1020RDB and P1011RDB
* MPC8641D and MPC8641

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Poonam Aggrwal
58442dc01e ppc/85xx,86xx: Handling Unknown SOC version
Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Kumar Gala
5052a771cf ppc/85xx: Cleanup makefile and related optional files
Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases
we have like PCI, CPM2, QE.  Also reworked it to use one line per file
for everything and sorted in alphabetical order.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:07 -05:00
Kumar Gala
c725908681 ppc/85xx: Fix bug in setup_mp code
Its possible that we try and copy the boot page code out of flash into a
DDR location that doesn't have a TLB cover it.  For example, if we have
3G of DDR we typically only map the first 2G.  In the cases of 4G+ this
wasn't an issue since the reset page TLB mapping covered the last page
of memory which we wanted to copy to.

We now change the physical address of the reset page TLB to map to the
true physical location of the boot page code, copy and than set the
TLB back to its 1:1 mapping of the reset page.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:06 -05:00
Kumar Gala
c2287af155 ppc/85xx: Add a simple function to search the TLB
Allow us to search the TLB array based on an address.  This is useful
if we want to change an entry but dont know where it happens to be
located.

For example, the boot page mapping we use on MP or the flash TLB that
we change the WIMGE settings for after we've relocated.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:05 -05:00
Kumar Gala
26f4cdba6b 85xx: Add support for setting IVORs to fixed offset defaults
In future Book-E implementations IVORs will most likely go away and be
replaced with fixed offsets.  The IVPR will continue to exist to allow
for relocation of the interrupt vectors.

This code adds support to setup the IVORs as their fixed offset values
per the ISA 2.06 spec when we transition from u-boot to another OS
either via 'bootm' or a cpu release.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:05 -05:00
Dipen Dudhat
da1cd955df ppc/85xx: Fix up eSDHC controller clock frequency in the device tree
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:04 -05:00
Kumar Gala
2abbd31da6 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:04 -05:00
Dipen Dudhat
6b9ea08c50 ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a
platform define.  This will enable all the 85xx platforms to use sdhc_clk
based on CONFIG_FSL_ESDHC.

Signed-off-by: Gao Guanhua <B22826@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:02 -05:00
Timur Tabi
05f6f66474 85xx: Improve MPIC initialization
The MPIC initialization code for Freescale e500 CPUs was not using I/O
accessors, and it was not issuing a read-back to the MPIC after setting
mixed mode.  This may be the cause of a spurious interrupt on some systems.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:43 -05:00
Poonam Aggrwal
a713ba926b 85xx: Added single core members of FSL P1xx/P2xx processors series
P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Mingkai Hu
76b474e2f5 85xx: Add L2SRAM Register's macro definition
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Kumar Gala
ec79d33b2c 85xx: Move to a common linker script
There are really no differences between all the 85xx linker scripts so
we can just move to a single common one.  Board code is still able to
override the common one if need be.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Poonam Aggrwal
87c7661b42 85xx: Added P1020 Processor Support.
P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Poonam Aggrwal
0e870980a6 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Poonam Aggrwal
18bacc2027 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Kumar Gala
53efa1f1ac 85xx: Remove redudant PLATFORM_CPPFLAGS
For historic reasons we had defined some additional PLATFORM_CPPFLAGS
like:

PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1

However these are all captured in the config.h and thus redudant.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:37 -05:00
Wolfgang Denk
963f2f6117 Prepare 2009.08-rc3
Update CHANGELOG, minor Coding Style cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-08-22 23:27:26 +02:00
Kumar Gala
e393e2e9bc 85xx: Fix addrmap to include memory
When we init the addrmap based on the TLB we will not end up getting
the TLB that covers memory if we are using SPD.  The reason is we
haven't relocated at the point that we setup the memory TLB and thus it
will not get setup in the addrmap.

Instead we can just walk over the TLB array after we've relocated and
see all the TLBs that have been set and use that information to populate
the initial addrmap.  By doing this we insure that we get the TLB
entries that cover memory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-14 17:42:05 -05:00
Kumar Gala
4c2e3da82d Update Freescale copyrights to remove "All Rights Reserved"
"All Rights Reserved" conflicts with the GPL.

Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
2009-07-29 09:59:22 +02:00
Peter Tyser
0d595f76bc fsl_dma: Break out common memory initialization function
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01 23:12:01 -05:00
Peter Tyser
79f4333ceb 8xxx: Move dma_init() call to common code
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01 23:12:00 -05:00
Peter Tyser
191c711859 fsl_dma: Move dma function prototypes to common header file
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01 23:11:52 -05:00
Peter Tyser
7892f619d4 8xxx: Rename dma_xfer() to dmacpy()
Also update dmacpy()'s argument order to match memcpy's and use
phys_addr_t/phy_size_t for address/size arguments

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01 23:07:47 -05:00
Peter Tyser
017f11f68e 8xxx: Break out DMA code to a common file
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01 23:01:51 -05:00
Peter Tyser
2f21ce4d54 fsl/85xx, 86xx: Sync up DMA code
The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:17:58 -05:00
Peter Tyser
b1f12650d3 fsl: Create common fsl_dma.h for 85xx and 86xx cpus
Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:17:45 -05:00
Haiying Wang
8e55258f14 qe: Pass in uec_info struct through uec_initialize
The uec driver contains code to hard code configuration information for the uec
ethernet controllers. This patch creates an array of uec_info structures, which
are then parsed by the corresponding driver instance to determine configuration.
It also creates function uec_standard_init() to initialize all UEC interfaces
for 83xx and 85xx.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:17:02 -05:00