Commit graph

192 commits

Author SHA1 Message Date
Simon Glass
47cb8c654b sandbox: cros_ec: Add Kconfig for sandbox EC config
Move CONFIG_CROS_EC_SANDBOX to Kconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
3fbb78711c cros_ec: exynos: Match up device tree with kernel version
The U-Boot device trees are slightly different in a few places. Adjust them
to remove most of the differences. Note that U-Boot does not support the
concept of interrupts as distinct from GPIOs, so this difference remains.

For sandbox, use the same keyboard file as for ARM boards and drop the
host emulation bus which seems redundant.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
60f37fc6aa cros_ec: Drop unused CONFIG_DM_CROS_EC
Since all supported boards enable this option now, we can remove it along
with the old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
e96fc7dfc8 cros_ec: Reinit the cros_ec device when 'crosec init' is used
This command is supposed to reinit the device. At present with driver
model is does nothing. Implement this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
72a38e06a2 dm: cros_ec: Convert cros_ec LPC driver to driver model
This is the last driver to be converted. It requires an LPC bus and a
special check_version() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
a33aca10ac dm: sandbox: pci: Enable PCI for sandbox
Enable PCI options so that sandbox can be used for testing this bus with
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:07 -06:00
Simon Glass
d2cb9b2b00 dm: sandbox: Add a emulated PCI device as an example
This device sits on the sandbox PCI bus and provides a case-swapping
service for sandbox. It illustrates the use of both PCI I/O and PCI
memory accesses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:09:45 -06:00
Simon Glass
e564f054af dm: core: Add dev_get_uclass_priv() to access uclass private data
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:42 -06:00
gaurav rana
fe78378d7d fsl_sec_mon: Add driver for Security Monitor block of Freescale
The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.

The API's for transition of Security states have been added
which will be used in case of SECURE BOOT.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-05 12:04:59 -08:00
Simon Glass
6fb9ac15eb dm: cros_ec: Convert to Kconfig
Since both I2C and SPI are converted to Kconfig, we can convert cros_ec
to Kconfig for these buses.

LPC will need to wait until driver mode PCI is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-19 06:19:18 -07:00
Simon Glass
f94a1bed07 dm: Expand and complete Kconfig in drivers/
Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-12 10:35:33 -07:00
Simon Glass
85df958ce2 dm: cros_ec: Convert cros_ec_i2c over to driver model
Move this driver to use driver model and update the snow configuration to
match.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:10:01 -07:00
Simon Glass
b2568f0d57 dm: cros_ec_spi: Remove old pre-driver-model code
This is no-longer needed since all platforms use SPI for cros_ec.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:57 -07:00
Simon Glass
8bbb38b15f dm: cros_ec: Don't require protocol 3 support
I2C is now deprecated on ARM platforms and there are no devices that use it
with the v3 protocol. We can't require v3 support if we want to support I2C.
Adjust the error handling to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:57 -07:00
Simon Glass
d0cff03e18 dm: spi: Move slave details to child platdata
At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually know what chip select it will appear on.

However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the chip select when the child is bound,
and avoid the messy contortions.

Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:56 -07:00
Simon Glass
32f8a19f6d dm: cros_ec: Remove use of fdtdec GPIO support
These functions are going away, so use the new uclass support instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:51 -07:00
Masahiro Yamada
ee5ee87642 i2c_eeprom: include <linux/err.h> to fix build error
drivers/misc/i2c_eeprom.c fails to build unless CONFIG_FIT_SIGNATURE
is defined.

  CC      drivers/misc/i2c_eeprom.o
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read':
drivers/misc/i2c_eeprom.c:15:10: error: 'ENODEV' undeclared
(first use in this function)
drivers/misc/i2c_eeprom.c:15:10: note: each undeclared identifier
is reported only once for each function it appears in
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_write':
drivers/misc/i2c_eeprom.c:21:10: error: 'ENODEV' undeclared
(first use in this function)
drivers/misc/i2c_eeprom.c:22:1: warning: control reaches end of
non-void function [-Wreturn-type]
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read':
drivers/misc/i2c_eeprom.c:16:1: warning: control reaches end of
non-void function [-Wreturn-type]
make[2]: *** [drivers/misc/i2c_eeprom.o] Error 1
make[1]: *** [drivers/misc] Error 2
make: *** [drivers] Error 2

By the way, Sandbox (enabling CONFIG_FIT_SIGNATURE) is luckily
working depending on it.
Sandbox includes include/asm-generic/errno.h
            from include/errno.h
            from include/u-boot/rsa-checksum.h
            from include/image.h
            from include/common.h
            from drivers/misc/i2c_eeprom.c

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-05 17:45:15 -07:00
Bin Meng
a2927e09bc x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Simon Glass
20142019a9 dm: Add a simple EEPROM driver
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:43 -07:00
Simon Glass
6ec1b75358 dm: i2c: Add an I2C EEPROM simulator
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Fabio Estevam
a847fff11c mxc_ocotp: Do not disable the OCOTP clock after every access
Leave the OCOTP turned on, so that we subsequent access do not fail.

After enabling the thermal driver on a mx6sxsabresd board:

U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
CPU:   Temperature 48 C
Reset cause: POR
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
  00:01.0     - 16c3:abcd - Bridge device
   01:00.0    - 8086:08b1 - Network controller
In:    serial
Out:   serial
Err:   serial
Net:
(hang)

As the thermal driver accesses the ocotp registers, its clock will be disabled
afterwards.

Then when the MAC address is read (also from ocotp registers) it will cause a
hang.

Do not disable the ocotp clock to prevent this problem.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2014-12-01 10:20:19 +01:00
Hector Palacios
3d99fcbc15 mxs_ocotp: clear the error flag before initiating write operation
A previous operation may have set the error flag, which must be cleared
before a new write operation can be issued.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2014-12-01 10:19:42 +01:00
Hector Palacios
ad5dd7ae4b mxs_ocotp: check for errors from the OTP controller after writing
The write operation may fail when trying to write to a locked area. In
this case the ERROR bit is set in the CTRL register. Check for that
condition and return an error.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-01 10:19:41 +01:00
Hector Palacios
d8d160e420 mxs_ocotp: prevent error path from returning success
The code may goto 'fail' upon error with 'ret' variable set to an error
code, but this variable was being overwritten by a final preparation
function to restore the HCLK, so success was (in general) returned even
after an error was hit previously.

With this change, the function may now return success even if the final
preparation function fails, but it's probably enough to print a message
because (if successful) the real programming of the fuses has already
completed.

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2014-12-01 10:19:41 +01:00
Tom Rini
1739564e75 Merge git://git.denx.de/u-boot-dm
Conflicts:
	drivers/serial/serial-uclass.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-24 12:01:48 -05:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Simon Glass
d11e8fd86e cros_ec: Fix uninitialised variable in cros_ec.c
This fixes this cppcheck report:

[drivers/misc/cros_ec.c:704]: (error) Uninitialized variable: req

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Denk <wd@denx.de>
2014-11-22 10:16:48 +01:00
Masahiro Yamada
4515992fc7 replace DIV_ROUND with DIV_ROUND_CLOSEST
The Linux-compatible macro DIV_ROUND_CLOSEST is a bit more flexible
and safer than DIV_ROUND.

For example,
  foo = DIV_ROUND_CLOSEST(x, y++)
works expectedly, but
  foo = DIV_ROUND(x, y++)
does not. (y is incremented twice.)

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-20 11:28:25 -05:00
Tom Rini
dee8abcd80 Merge git://git.denx.de/u-boot-x86 2014-10-23 06:54:03 -04:00
Simon Glass
f1269925f9 x86: cros_ec: Update LPC driver for new cros_ec header
There was a minor rename of one of the defines, so update the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 21:50:32 -06:00
Simon Glass
ea0ebc8662 dm: exynos: cros_ec: Move cros_ec_spi to driver model
Adjust this driver to use driver model and move smdk5420 boards over to
use it.

Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:53 -06:00
Simon Glass
be995a8545 dm: sandbox: cros_ec: Move sandbox cros_ec to driver module
Adjust the sandbox cros_ec emulation driver to work with driver model, and
switch over to driver model for sandbox cros_ec.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:53 -06:00
Simon Glass
84d6cbd302 dm: cros_ec: Add support for driver model
Add support for driver model if enabled. This involves minimal changes
to the code, mostly just plumbing around the edges.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:53 -06:00
Masahiro Yamada
ed36323f6d kconfig: add blank Kconfig files
This would be useful to start moving various config options.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-09-24 18:30:28 -04:00
Simon Glass
2001b9a641 cros_ec: Fix two bugs in the SPI implementation
An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
709ea543b9 stdio: Pass device pointer to stdio methods
At present stdio device functions do not get any clue as to which stdio
device is being acted on. Some implementations go to great lengths to work
around this, such as defining a whole separate set of functions for each
possible device.

For driver model we need to associate a stdio_dev with a device. It doesn't
seem possible to continue with this work-around approach.

Instead, add a stdio_dev pointer to each of the stdio member functions.

Note: The serial drivers have the same problem, but it is not strictly
necessary to fix that to get driver model running. Also, if we convert
serial over to driver model the problem will go away.

Code size increases by 244 bytes for Thumb2 and 428 for PowerPC.

22: stdio: Pass device pointer to stdio methods
       arm: (for 2/2 boards)  all +244.0  bss -4.0  text +248.0
   powerpc: (for 1/1 boards)  all +428.0  text +428.0

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:23 +01:00
Jeroen Hofstee
2b9912e6a7 includes: move openssl headers to include/u-boot
commit 18b06652cd "tools: include u-boot version of sha256.h"
unconditionally forced the sha256.h from u-boot to be used
for tools instead of the host version. This is fragile though
as it will also include the host version. Therefore move it
to include/u-boot to join u-boot/md5.h etc which were renamed
for the same reason.

cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-06-19 11:19:04 -04:00
York Sun
e77224e2d8 driver/fsl_ifc: Add a function to finalize CS0 address binding
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
to higher address to support large space.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-04-22 17:58:47 -07:00
Stefano Babic
1cad23c5f4 Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-04 11:35:30 +02:00
Marek Vasut
2bbcccf552 ARM: mxs: Add OCOTP driver
Add yet another OCOTP driver for this i.MX family. This time, it's a driver for
the OCOTP variant found in the i.MX23 and i.MX28. This version of OCOTP is too
different from the i.MX6 one that I could not use the mxc_ocotp.c driver without
making it into a big pile of #ifdef . This driver implements the regular fuse
command interface, but due to the IP blocks' limitation, we support only READ
and PROG functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-03-31 18:28:50 +02:00
Simon Glass
b2a668b523 cros_ec: Implement I2C pass-through
The Chrome EC has a feature where you can access its I2C buses through a
pass-through arrangement. Add a command to support this, and export the
function for it also.

Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:48 -06:00
Simon Glass
df93d90aea cros_ec: sandbox: Add Chrome OS EC emulation
Add a simple emulation of the Chrome OS EC for sandbox, so that it can
perform various EC tasks such as keyboard handling.

Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
2ab83f0d75 cros_ec: Correct comparison between signed and unsigned numbers
Due to signed/unsigned comparison, '< sizeof(struct)' does not do the right
thing, since if ec_command() returns a -ve number we will consider this be
success.

Adjust all comparisons to avoid this problem.

This error was found with sandbox, which gives a segfault in this case. On
ARM we may instead silently fail.

We should also consider turning on -Wsign-compare to catch this sort of thing
in future.

Reviewed-by: Andrew Chew <achew@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
2014-03-17 20:05:47 -06:00
Randall Spangler
a607028331 cros_ec: spi: Add support for EC protocol version 3
Protocol version 3 will be attempted first; if the EC doesn't support
it, u-boot will fall back to the old protocol version (2).

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
2d8ede58ca cros_ec: Add base support for protocol v3
Protocol v2 was shipped with snow, link and spring. Protocol v3 is for
pit and is targetted at SPI operation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Randall Spangler
e8c1266236 cros_ec: Clean up multiple EC protocol support
Version 1 protocols (without command version) were already no longer
supported in cros_ec.c.  This removes some dead code from the
cros_ec_i2c driver.

Version 2 protcols (with command version) are now called
protocol_version=2, instead of cmd_version_is_supported=1.

A subsequent change will introduce protocol version 3 for SPI.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
836bb6e827 cros_ec: Sync up with latest Chrome OS EC version
The EC messages have been expanded and some parts have been renamed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
1c266b9214 cros_ec: Move #ifdef to permit flash region access
Flash region access is not tied to having commands, so adjust the #ifdef
to reflect this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:46 -06:00
Vadim Bendebury
4ff9b461a8 cros_ec: Drop old EC version support from EC driver
There is no need to support old style EC moving forward. Ultimately we
should get rid of the check_version() API. For now just return error
in case the EC does not seem to support the new API.

Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Tested-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:46 -06:00
Simon Glass
d7f25f35f4 cros_ec: Add a function for decoding the Chrome OS EC flashmap
In order to talk to the EC properly we need to be able to understand the
layout of its internal flash memory. This permits emulation of the EC
for sandbox, and also software update in a system with a real EC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:46 -06:00
Albert ARIBAUD
a891601ce5 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
2014-01-06 08:49:58 +01:00
Sergey Alyoshin
4611d5bab2 arm: mx5: Add fuse supply enable in fsl_iim
Enable fuse supply before fuse programming and disable after.

Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2014-01-03 15:44:06 +01:00
Simon Glass
0efc02499f spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT node
This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-12-09 12:22:12 -07:00
Tom Rini
77fdd6d1eb Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-12-02 08:38:28 -05:00
York Sun
0b66513b27 Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
Igor Grinberg
9dfdcdfed4 gpio_led: add support for inverted polarity
Some GPIO connected LEDs have inverted polarity.
Introduce new config option: CONFIG_GPIO_LED_INVERTED_TABLE for the
specifying the inverted GPIO LEDs list and add support for this in the
gpio_led driver.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Ilya Ledvich <ilya@compulab.co.il>
2013-11-25 10:41:52 -05:00
Igor Grinberg
6516f81b64 gpio_led: check gpio_request() return value
Add a check for the gpio_request() function return value and do not try
to configure the GPIO if the gpio_request() call fails.
Also, print an error message indicating the gpio_request() has failed.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Ilya Ledvich <ilya@compulab.co.il>
2013-11-25 10:41:52 -05:00
Masahiro Yamada
710f1d3d5f drivers: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:26:01 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Hung-ying Tyan
c8d3328a0a cros: add LPC support for cros_ec
This patch adds LPC support for carrying out the cros_ec protocol.

Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:13:28 -04:00
Hung-ying Tyan
f3424c554c cros: exynos: add SPI support for cros_ec
This patch adds SPI support for carrying out the cros_ec protocol.

Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:13:24 -04:00
Hung-ying Tyan
78764a4e11 cros: add I2C support for cros_ec
This patch adds I2C support for carrying out the cros_ec protocol.

Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:12:24 -04:00
Hung-ying Tyan
88364387c6 cros: add cros_ec driver
This patch adds the cros_ec driver that implements the protocol for
communicating with Google's ChromeOS embedded controller.

Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:07:11 -04:00
Albert ARIBAUD
cac423a730 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-05-11 22:24:28 +02:00
Nishanth Menon
0208aaf6c2 twl4030: make twl4030_i2c_write_u8 prototype consistent
u-boot standard i2c register write prototype is
i2c_reg_write(u8 addr, u8 reg, u8 val)

twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val)

Signed-off-by: Nishanth Menon <nm@ti.com>
2013-05-10 08:25:54 -04:00
Benoît Thébaudeau
112fd2ec6c Add mxc_ocotp driver
Add an mxc_ocotp driver for i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:43 +02:00
Benoît Thébaudeau
0f67e09e9e Add fsl_iim driver
Add a fsl_iim driver common to i.MX and MPC.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:41 +02:00
Vadim Bendebury
b012bc94ac x86: Add console command to display CBMEM console buffer
This command is useful to allow to observe messages generated by
coreboot and u-boot until present. In particular it is handy when
u-boot is instrumented to fall through into console mode on startup
errors.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:03 -08:00
Vadim Bendebury
98ab435f73 x86: Add CBMEM console driver for coreboot
This patch builds upon the recently introduced CBMEM console
feature of coreboot.

CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.

Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.

>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:

vvvvvvvvvvvvvvvvv
SCSI:  AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure  quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^

Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:03 -08:00
Scott Wood
8bc50f0b6d powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx
It's arch code and not a driver, so move it where it belongs.  When it
originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Łukasz Majewski
e0a0cbf247 pmic: Move pmic related code to ./drivers/power directory
The PMIC framework has been moved to its more natural place
./drivers/power from ./drivers/misc directory.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-11-14 11:21:09 +01:00
Łukasz Majewski
c733681507 pmic: Extend PMIC framework to support multiple instances of PMIC devices
The PMIC framework has been extended to support multiple instances of
the variety of devices responsible for power management.
This change allows supporting of e.g. fuel gauge, charger, MUIC (Micro USB
Interface Circuit).
Power related includes have been moved to ./include/power directory.
This is a first of a series of patches - in the future "pmic" will be
replaced with "power".

Two important issues:
1. The PMIC needs to be initialized just after malloc is configured
2. It uses list to hold information about available PMIC devices

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-14 11:21:09 +01:00
Łukasz Majewski
452329f1d5 pmic:max8997: Switch the MAX8997 PMIC to be used with multibus I2C
PMIC MAX8997 is now ready to work with single and multibus soft I2C
implementation.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-11-14 11:21:07 +01:00
Łukasz Majewski
86879d7120 pmic:i2c: Add I2C sensor byte order (big/little) to PMIC framework
Since the pmic_reg_read is the u32 value, the order in which bytes
are placed to form u32 value is important.

Support for big and little sensor endianess is added.

Moreover calls to [leXX|beXX]_to_cpu have been added to support
little and big endian SoCs.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-11-14 11:21:07 +01:00
Łukasz Majewski
b5bf9cafea pmic:i2c: Handle PMIC I2C transmission comprising of two bytes
This patch adds support for proper handling of a PMIC I2C transmission
comprising of two bytes.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-14 11:21:07 +01:00
Liu Gang
461632bd71 powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.

NOTE: Because the slave can not erase, write master's NOR flash by
	  PCIE interface, so it can not modify the ENV parameters stored
	  in master's NOR flash using "saveenv" or other commands.

environment and requirement:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image is in master NOR flash.
	3. Put the slave's ucode and ENV into it's own memory space.
	4. Normally boot from local NOR flash.
	5. Configure PCIE system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to one PCIE interface by RCW.
	3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the slave module, need to finish these processes:
	1. Set the boot location to one PCIE interface by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID of one PCIE for the boot.
	4. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	5. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	6. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
	1. Updated the README.srio-boot-corenet to add descriptions about
	   boot from PCIE, and change the name to
	   README.srio-pcie-boot-corenet.
	2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
	   "xxxx_SRIO_PCIE_BOOT", and the image builded with
	   "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
	   from PCIE.
	3. Updated other macros and documents if needed to add information
	   about boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:15 -05:00
Liu Gang
81fa73bab0 powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
Fabio Estevam
ed5157e889 pmic: dialog: Avoid name conflicts
As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC,
we need to be able to build both drivers.

Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Fabio Estevam
20831061d8 pmic: Add support for the Dialog DA9053 PMIC
Add support for the Dialog DA9053 PMIC.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:31 +02:00
Łukasz Majewski
8504296045 misc:pmic:max8997 MAX8997 support for PMIC driver
This commit adds support for MAX8997 PMIC driver.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:29 +02:00
Fabio Estevam
a22429d2bf pmic_i2c: Return error in case of invalid pmic_i2c_tx_num
Return error in case of invalid pmic_i2c_tx_num.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-03-27 09:41:16 +02:00
Helmut Raiger
435a728587 misc: pmic: fix regression in pmic_fsl.c (SPI)
This fixes write access to PMIC registers, the bug was
introduced partly in commit 64aac65099 and in commit c9fe76dd91.
It was tested on an i.mx31 with a mc13783.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:18 +01:00
Stefano Babic
f8f96129bf misc: pmic: drop old Freescale's pmic driver
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:32 +02:00
Stefano Babic
b7b7d3ccfd misc: pmic: addI2C support to pmic_fsl driver
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:31 +02:00
Stefano Babic
d69edadee7 misc: pmic: use I2C_SET_BUS in pmic I2C
Instead of using directly the i2c_set_bus() function,
the I2C_SET_BUS macro must be used to avoid build
errors for targets without multibus I2C.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:31 +02:00
Stefano Babic
b2e5add3b2 misc: pmic: Freescale PMIC switches to generic PMIC driver
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:31 +02:00
Łukasz Majewski
993858585d misc:pmic:max8998 MAX8998 support at a new PMIC driver.
This commit adds support for MAX8998 PMIC driver.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:31 +02:00
Łukasz Majewski
e542b7f0a2 misc:pmic:core New generic PMIC driver
I2C or SPI PMIC devices can be accessed.
Separate files: pmic_i2c.c and pmic_spi.c are responsible
for handling transmission over I2C or SPI bus.

New flags:
CONFIG_PMIC - enable PMIC general device.
CONFIG_PMIC_I2C/SPI - specify the interface to be used.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:31 +02:00
Jason Liu
50cf807343 cosmetic: fsl_pmic: cosmetic for the help message
This is cosmetic patch for the help message:

Before:
pmic dump [numregs] dump registers
After:
pmic dump [numregs] - dump registers

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-09-30 22:01:00 +02:00
Albert ARIBAUD
fa82f871c8 Convert ISO-8859 files to UTF-8
There was a mix of UTF-8 and ISO-8859 files in the U-Boot source
tree, which could cause issues with the patchwork review system.
This commit converts all ISO-8859 files to UTF-8.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-08-04 23:34:02 +02:00
Wolfgang Denk
cd6881b519 Minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-05-19 22:22:44 +02:00
Kumar Gala
7639675131 powerpc/8xxx: Fix LAW init to respect pre-initialized entries
If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.

In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Kumar Gala
8e29ebabf8 fsl_law: Fix LAW printing function
We had an extra '0x' in the output of the LAWAR header that would cause
output like:

LAWBAR11: 0x00000000 LAWAR0x11: 0x80f0001d

intead of:

LAWBAR11: 0x00000000 LAWAR11: 0x80f0001d

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-22 23:25:19 -06:00
Stefano Babic
01bb24b642 Add basic support for Freescale's mc9sdz60
The patch adds helper funtions for basic access to the registers
of the MC9sdz60 chip (multifunctional device with RTC and CAN) via
I2C interface.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-02-02 00:54:43 +01:00
Liu Hui-R64343
3382fd48f2 fsl_pmic: add I2C interface support
This patch add I2C interface for fsl_pmic driver support

Signed-off-by: Jason Liu <r64343@freescale.com>
2011-02-02 00:54:42 +01:00
Kumar Gala
243be8e296 powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers
Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.

Eventually this should be handled by Kconfig & defconfigs

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-19 22:58:23 -06:00
Kumar Gala
f193e3da98 powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Poonam Aggrwal
b5debec5b5 powerpc/85xx: Add Support for Freescale P1014 Processor
The P1014 is similar to the P1010 processor with the following differences:

- 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC)
- no eCAN interface. (P1010 has 2 eCAN interfaces)
- Two SGMII interface (P1010 has 3 SGMII)
- No secure boot

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Poonam Aggrwal
b8cdd01462 powerpc/85xx: Add Support for Freescale P1010 Processor
Key Features include of the P1010:
* e500v2 core frequency operation of 500 to 800 MHz
* Power consumption less than 5.0 W at 800 MHz core speed
* Dual SATA 3 Gbps controllers with integrated PHY
* Dual PCI Express controllers
* Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs)
	* TCP/IP acceleration and classification capabilities
	* IEEE 1588 support
	* Lossless flow control
	* RGMII, SGMII
* DDR3 with support for a 32-bit data interface (40 bits including ECC),
  up to 800 MHz data rate 32/16-bit DDR3 memory controller
* Dedicated security engine featuring trusted boot
* TDM interface
* Dual controller area networks (FlexCAN) controller
* SD/MMC card controller supporting booting from Flash cards
* USB 2.0 host and device controller with an on-chip, high-speed PHY
* Integrated Flash controller (IFC)
* Power Management Controller (PMC)
* Four-channel, general-purpose DMA controller
* I2C controller
* Serial peripheral interface (SPI) controller with master and slave support
* System timers including a periodic interrupt timer, real-time clock,
  software watchdog timer, and four general-purpose timers
* Dual DUARTs

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00