Commit graph

244 commits

Author SHA1 Message Date
Tom Rini
10d3e90f46 Two fixes for the Amlogic Pinctrl driver :
- bad usage of clrsetbits_le32
 - bad pin definition for AXG Family
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJcCkUAAAoJEHfc29rIyEnRqtAP/2BpLCNUqeZXzgaTueFbSp6z
 JYPL45POLunaZrlTHVCrYTymcqr+AuS1cPjEIZI49RgVepDs6EWR/NcLWexiFKZ8
 kdxSVP8FO6675sJ8KdYzGbgdBna5a2HPWZtYmX0OHGKgiPClL9HAkGrFWAwJtlHK
 2zAQ+zRPt4TTwEgkmKK2/38Jz7rgkIpeXWoSuu9UEGmfkMhNFLGOPbzzNxHJTL3n
 Ll7hLjLTBexgS6FQSHlNOj4XOnUubGTCchblCuMeVrEmUnvsgsXkzNMpRvfClzsZ
 YsFgRHikTZG56QoUKErGu1XeJweF1DPQsYuxRQf4YJBjAiGHw0ASNgMy1cFmSfUp
 rRCPDm4RHbSAvg/26iEU62FyFFLfrbtYuQJoxvp9iQbeamdXzFg/m8FyW4lNUeMU
 xO42XobtsmEahsSlxPB9akIJEWOLNLXFt/HHCqHJZYGRu5wDK5ZysTp2E2sHCYF8
 zttTi8WoPfiClmo8bLTIW/2SLylYILn48b9Gw6uZUq9B2uhsVeEro6Ya0d/fkFUd
 IbtqGmcG/ejsh6R4V1BEHr96KEcpgXAzzWTW0IPGZIyQ4VHq+bOhL/YPm5eX2WVW
 Wq/qMmhXuoJpZP/l/b3B4xRhQ5JWjWPtd8C2QBBTOX8uCSbmS0z+r6s0CTDzesD+
 ODiWDH021RxK7WiJV4kN
 =dvG1
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20181207' of git://git.denx.de/u-boot-amlogic

Two fixes for the Amlogic Pinctrl driver :
- bad usage of clrsetbits_le32
- bad pin definition for AXG Family
2018-12-07 19:01:09 -05:00
Patrice Chotard
530b63c228 pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev()
Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must
be updated.

stm32_pinctrl_get_gpio_dev() returns from a given pin selectors
the corresponding bank gpio device and the gpio_offset inside this
gpio bank.

Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:48 -05:00
Patrice Chotard
043550415b pinctrl: stm32: Move gpio_dev list filling outside probe()
Move gpio_dev list filling outside probe() to speed-up U-boot
boot sequence execution. This list is populated only when needed.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Carlo Caione
139ebe9eb9 pinctrl: meson: axg: Fix GPIO pin offsets
The pin number (first and last) in the bank definition is missing the
pin base offset shifting. This is causing a miscalculation when
retrieving the register and pin offsets in the GPIO driver causing the
'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip
(the AO bank is driven correctly because the shifting is already 0).

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-07 11:01:09 +01:00
Benjamin Gaignard
075b0185b6 pinctrl: stm32: make pinctrl use hwspinlock
Protect configuration registers with a hardware spinlock.

If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06 23:26:33 -05:00
Carlo Caione
fb19c7bade pinctrl: meson: Fix GPIO direction registers access
The macros used to set the direction of the GPIO pins are misused,
resulting in a wrong behavior when trying to read the GPIO input level
from U-Boot.

A better macro is also used when setting the output direction.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-05 10:39:17 +01:00
Tom Rini
93e72ac472 Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
 - net: designware: add meson meson compatibles
 - Amlogic Meson cleanup for AXG SoC support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJb/AwoAAoJEHfc29rIyEnR2dMQANCsuWQzKASCLgUzeL/KWhQ8
 gj1YEVGbS0meQ35hNo0hL6qfN4VkjazawyWnb40HVVADBjil42QuxN9rncovg69Q
 ZvPEo4XYNCkDzOU3UmoR2rjxxGICVFY6GCOuNbqzvB2x4gWJmoUeByqewKW2g2Zp
 jyjbzYvJ+r8wLtUFbdqaGvsHHC8hiIkjyeaqdXUc6NHJrGYasRuOsCO92bEioYC1
 XPh76c2ABAnbzJy7GArdlBbDOQrQxoEskVeP47ZjiPywXxGCkgHaRSXaUKzpz30G
 8MrA5AciL6pmurmsM0APlgvJwL7qaX1P6NxiJ+12prWWfAk1ZC2/MEKVZY+gO/CF
 vUAyzhus1oJ5JjccCngy/1ftkIReueSbUrzGYFvqhihs9g4QyRpi7F5MDKX0MvP2
 uk+XXStXs+rOZ2YdMFlV8l6G12TijcViZVmVHdh8qdl4t8WFlv7gENVUM+0mhyu2
 x5OsoYz5w2h9hCh/CB3oIZfyJBe5VZVHZ2fWIRZJ72J7toUGMewlKYQq2LOv7A9q
 w6vRGnza3fSPUZgYenznohaeo9vXG/WX7cNSPQiNBoiGeC+Y2ko5NHe2MIEnUD4c
 amp21KA6rWnWeHHvDbwo5DJ+NhCd6uMgkiZDLCuiTtns1/a03l0V6kgOvQLIBjhK
 KxBWBn6+rDPq1wJxhxab
 =Oo1g
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
2018-11-29 15:16:58 -05:00
Ryder Lee
59a8fef342 pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Ryder Lee
01aa9d1d54 pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Jerome Brunet
8587839f19 pinctrl: meson: add axg support
This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
using a specific set of pinctrl functions which differs from the GX SoCs.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
2f9a38b50f pinctrl: meson: select generic pinctrl
Meson pinctrl needs generic pinctrl, rather than depending on it
select it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
7c9dcfed50 pinctrl: meson: rework gx pmx function
In preparation of supporting the new Amlogix AGX SoCs, we need to move
the Amlogic GX pinmux functions out of the common code to be able to
add a different set of SoC specific pinmux functions for AXG.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Patrice Chotard
21e23aaff6 pinctrl: sandbox: Add get_pin_muxing ops support
Add get_pin_mux ops support to display the pin muxing
description of the sandbox_pins[]

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-16 16:51:57 -05:00
Patrice Chotard
b42d938c24 pinctrl: stm32: Add get_pin_muxing() ops
Add get_pin_muxing() ops to obtain the pin muxing description
a given pin index.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-16 16:51:56 -05:00
Patrice Chotard
4ff1c20b92 pinctrl: stm32: Add get_pin_name() ops
Add get_pin_name ops to obtain a pin name given a
pin index of a specified pin-controller.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-16 16:51:56 -05:00
Patrice Chotard
8f651ca60b pinctrl: stm32: Add get_pins_count() ops
Add get_pins_count ops to obtain the number of pins
owns by a pin-controller.
On STM32 SoCs bindings, each pin-controller owns
several gpio banks. Each GPIO bank can own up to 16 pins.

To obtain the total pins count, walk through each sub-nodes
(ie GPIO banks) and sum each GPIO banks pins number. For that
in probe() we build a list with each GPIO device reference found.
This list will also be used with future get_pin_muxing and get_pin_name
ops to speed up and optimize walk through all GPIO banks.

As this code is common to all STM32 SoCs, this code is put
under SPL_BUILD compilation flag to avoid to increase SPL code size
for STM32F7 which is limited to 32Ko.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-16 16:51:56 -05:00
Patrice Chotard
8bbb5b2085 dm: pinctrl: Add pinctrl_get_pin_name and pinctrl_get_pins_count
Add pinctrl_get_pin_name() and pinctrl_get_pins_count() methods
to obtain pin's name and pin's muxing given a pin reference.

This will be used by the new pinmux command.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-16 16:51:55 -05:00
Patrice Chotard
f55a0c0a20 dm: pinctrl: Add get_pin_muxing() ops
Add get_pin_muxing() which allows to display the muxing
of a given pin belonging to a pin-controller.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-16 16:51:55 -05:00
Bin Meng
ad0e804843 pinctrl: Remove DM_FLAG_PRE_RELOC flag in various drivers
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.

To mitigate this potential impact, the following changes are
implemented:

- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
  only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
  is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
  drivers that support both statically declared devices and
  configuration from device tree

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:28 -08:00
Marek Vasut
5dbdd3a600 pinctrl: renesas: Add POCCTRL handling to r8a77990
Add definition of the POCCTRL register and bits therein to R8A77990 E3
pincontrol driver. This allows the pincontrol driver to configure SDHI
pin voltage according to power-source DT property.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Marek Vasut
0ff9e4800f pinctrl: renesas: Fix DRV register offset
Use fixed 4bit size for generating the DRV register element mask,
not the size of the value, which can be smaller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Peng Fan
38b6686f05 pinctrl: Add pinctrl driver for i.MX8
Add pinctrl driver for i.MX8. The pads configuration is controlled
by SCU, so need to ask SCU to configure pads through scfw API.
Add pinctrl-scu to invoke sc_pad_set to configure pads.
Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms
which could directly configure pads from Acore side.
Add CONFIG_PINCTRL_IMX8 as the built gate.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Eugen Hristev
0523a6c6f7 pinctrl: sandbox: add gpio onewire w1 group
Add onewire "w1" groups and pin function for onewire GPIOs in sandbox.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:37 -04:00
Philippe Reynes
b3f8e88f3c pinctrl: bcm6838: add pinctrl support
Add pinctrl support for broadcom bcm6838 SoC.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-09-22 20:49:59 +02:00
Lokesh Vutla
5a07cf5e7a pinctrl: Fix build warning with ARM64
Following build warning appears when pinctrl-single is built for ARM64:

In file included from drivers/pinctrl/pinctrl-single.c:10:0:
drivers/pinctrl/pinctrl-single.c: In function ‘single_configure_pins’:
./arch/arm/include/asm/io.h:43:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
 #define __arch_getw(a)   (*(volatile unsigned short *)(a))

Fix this by using phys_addr_t for variable reg instead of u32

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-10 20:48:20 -04:00
Marek Vasut
5af6541972 pinctrl: renesas: Fix register usage in sh_pfc_{read,write}
The sh_pfc_{read,write}() must operate on the register address directly
rather than on an offset, fix this to prevent illegal access.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-19 06:15:55 +02:00
Marek Vasut
bf8d2dab38 pinctrl: renesas: Sync Gen3 PFC tables with Linux v4.17
Sync the PFC tables with Linux v4.17.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 22:35:21 +02:00
Marek Vasut
2e975d8628 pinctrl: renesas: Sync Gen2 PFC tables with Linux v4.17
Sync the PFC tables with Linux v4.17.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 13:36:33 +02:00
Tom Rini
040b2583c3 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-06-02 16:58:27 -04:00
Marek Vasut
cb13e46aeb pinctrl: renesas: Initial R8A77990 PFC support
This patch adds initial pinctrl driver to support for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:02 +02:00
Takeshi Kihara
634f9f0d30 pinctrl: renesas: Add PORT_GP_11 helper macro
This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:01 +02:00
Konstantin Porotchkin
f5db5979df mvebu: pinctrl: Add SD/eMMC PHY selector to the driver
When the pin control driver selects SD/eMMC function for
a pin group, there is additional configuration to be done
for this case - switch the PHY to work with SDHCI interface.
This patch adds the missing functionality into the pin
control driver.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Evan Wang <xswang@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29 08:33:05 +02:00
Evan Wang
f246648d37 mvebu: pinctrl: sync compatible string with Linux 4.17-rc4
For pinctrl driver of mvebu, the compatible strings
supported are defined differently from Linux version.
The patch aligned the compatible string with
Linux 4.17-rc4.

Signed-off-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29 08:33:05 +02:00
Kever Yang
f717b4c8e7 pinctrl: do not set_state for device without valid ofnode
Not all the udevice have a available DT node, eg. rksdmmc@ff500000.blk
which add by mmc_bind(), these device do not have/need set pinctrl
state.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-16 00:25:19 -06:00
Tom Rini
1ccd3f14ca Merge git://git.denx.de/u-boot-uniphier 2018-05-08 13:47:26 -04:00
Neil Armstrong
42de652272 pinctrl: meson: Update pinmux with new Linux bindings
The pinctrl bindings has changed for Amlogic Meson SoCs since Linux 4.13,
update the pinctrl driver to take this in account.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-05-08 09:07:34 -04:00
Masahiro Yamada
57a6c1bf87 pinctrl: uniphier: add ethernet TX pin data for LD20
These are necessary to optimize the drive-strength of the pins.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:15 +09:00
Masahiro Yamada
150997a44b pinctrl: uniphier: support drive-strength configuration
This allows our DT to specify drive-strength property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:15 +09:00
Masahiro Yamada
603fd9ead6 pinctrl: uniphier: support per-pin configuration via DT
Currently, the UniPhier pinctrl drivers expose only the pin-group
interface to device tree.

Provide .get_pins_count, .get_pin_name, .pinconf_set hooks to support
pin configuration via 'pins' DT property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:15 +09:00
Masahiro Yamada
03cfc80134 pinctrl: uniphier: include <linux/build_bug.h> instead of <linux/bug.h>
The #include <linux/bug.h> is here to use BUILD_BUG_ON_ZERO().

By replacing it with <linux/build_bug.h>, we can reduce the number of
headers pulled in.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:14 +09:00
Masahiro Yamada
7629d0b9bc pinctrl: uniphier: replace printf() with dev_err()
dev_err() is more suitable for printing error messages.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:14 +09:00
Masahiro Yamada
d5c0d9a12a pinctrl: uniphier: remove unneeded pin data of LD6b SoC
Since commit f73cfb4d0d ("pinctrl: uniphier: simplify input enable
and delete pin arrays"), these data are no longer used in any useful
way.  Remove.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-08 10:25:11 +09:00
Masahiro Yamada
8c1de5e08b regmap: clean up regmap allocation
Putting zero length array at the end of struct is a common technique
to embed arbitrary length of members.  There is no good reason to let
regmap_alloc_count() branch by "if (count <= 1)".

As far as I understood the code, regmap->base is an alias of
regmap->ranges[0].start, but it is not helpful but make the code
just ugly.

Rename regmap_alloc_count() to regmap_alloc() because the _count
suffix seems pointless.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: fixup cpu_info-rcar.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 15:15:27 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Tom Rini
0e5d3e3111 Merge git://git.denx.de/u-boot-dm 2018-04-01 20:36:39 -04:00
Kever Yang
1e656ad08c pinctrl-uclass: convert to use live dt
Use live dt interface for pinctrl_select_state_full()

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-31 15:59:59 +08:00
Tom Rini
f3b623fa52 Merge git://git.denx.de/u-boot-marvell 2018-03-30 18:18:22 -04:00
Ken Ma
dc36235abe arm64: a37xx: pinctrl: Correct mpp definitions
This patch corrects below mpp definitions:
 - The sdio_sb group is composed of 6 pins and not 5;
 - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
 - Pin of group "pmic0" is mpp1[6] but not mpp1[16];
 - Pin of group "pmic1" is mpp1[7] but not mpp1[17];
 - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
   bitmask is bit4;
 - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
   bit5 | bit9 | bit10 but not bit4;
 - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
   bit11 | bit12 | bit13.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43288
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30 12:52:48 +02:00
Ken Ma
0237448a71 arm64: a37xx: pinctrl: Fix gpio pin offset in register
For armada_37xx_update_reg(), the parameter offset should be pointer so
that it can be updated, otherwise offset will keep old value, and then
when offset is larger than or equal to 32 the mask calculated by
"BIT(offset)" will be 0 in gpio chip hook functions, it's an error,
this patch set offset parameter of armada_37xx_update_reg() as pointer.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30 12:52:48 +02:00