Commit graph

31 commits

Author SHA1 Message Date
David Dueck
da78fb5414 ARM: at91: atmel_nand: Support flash based BBT
Add support for on-flash bad block table. This makes U-Boot handle an existing
BBT correctly.

Signed-off-by: David Dueck <davidcdueck@googlemail.com>
Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Josh Wu <josh.wu@atmel.com>
CC: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
2015-04-01 01:04:28 +02:00
Wu, Josh
0e48dc5e41 mtd: atmel_nand: according to pmecc version to perform 0xff page correction
As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.

According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07 23:42:57 +01:00
Josh Wu
7df4486d04 mtd: atmel_nand: runtime to build gf table for pmecc
As in SAMA5D4 SoC, the gf table in ROM code can not be seen.
So, when we try to use PMECC, we need to build it when do
initialization.
Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it
is defined we will build gf table runtime.

The PMECC use the BCH algorithm, so based on the build_gf_tables()
function in lib/bch.c, we can build the Galois Field lookup table.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17 08:47:18 -05:00
Heiko Schocher
667af36905 spl, mtd, nand, atmel_nand: invert device ready pin logic
device ready pin is signalling that the device is ready on state 1
not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17 08:47:17 -05:00
Heiko Schocher
4dfd360589 spl, nand, atmel_nand: add erase one block function
erase one nand block in spl code. keep it simple, as size matters
This is used on the upcoming taurus spl support.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17 08:47:17 -05:00
Heiko Schocher
c1ec406282 mtd: atmel_nand: add missing include
using this driver in SPL code with CONFIG_SPL_NAND_ECC
configured leads in an compileerror. Fix this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17 08:47:17 -05:00
Boris BREZILLON
d357b94041 mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECC
Disable subpage write when using PMECC to prevent buggy partial page write.

This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:22 +02:00
Wu, Josh
14b3b44eda mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc register
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access.
But in the driver we also use the readl(b)/writel.
To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:13 +02:00
Brian Norris
27ce9e4290 mtd: nand: force NAND_CMD_READID onto 8-bit bus
As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

Thus porting  following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.

    commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
    mtd: nand: force NAND_CMD_READID onto 8-bit bus
    Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)

    The NAND command helpers tend to automatically shift the column address
    for x16 bus devices, since most commands expect a word address, not a
    byte address. The Read ID command, however, expects an 8-bit address
    (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
    0x20).

    This fixes the column address for a few drivers which imitate the
    nand_base defaults.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:03 -04:00
Bo Shen
0b0b4f5981 mtd: nand: atmel: prepare for nand spl boot support
Prepare for nand spl boot support. It supports nand software ECC and
hardware PMECC.
This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-03-09 19:19:06 +01:00
Albert ARIBAUD
f15ea6e1d6 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/armv7/rmobile/Makefile
	doc/README.scrapyard

Needed manual fix:
	arch/arm/cpu/armv7/omap-common/Makefile
	board/compulab/cm_t335/u-boot.lds
2013-12-10 22:23:59 +01:00
Andreas Bießmann
ac45bb1646 at91: nand: switch atmel_nand to generic GPIO API
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-12-09 13:21:45 +01:00
Wu, Josh
c0dc3dec69 mtd: atmel_nand: use dev_xxx instead of printk
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
c55cc573ea mtd: atmel_nand: don't print bit correction message in driver
Since for some MLC nand, bit errors happened too often. Just disable it
to avoid noise

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Wu, Josh
16dddef605 mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flash
increase the delay to 75us to support the 8k bytes page nand flash

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21 13:33:41 -06:00
Bo Shen
7604a3f920 MTD: atmel_nand: support for software BCH ECC
Add possible to use software BCH ECC for atmel nand driver

Signed-off-by: Bo Shen <voice.shen@gmail.com>
2013-11-13 17:20:26 -06:00
Wu, Josh
1bd3e2a823 mtd: atmel_nand: pmecc: fix bug fail to correct bit error in 1024-bytes sector
The PMECC use BCH algorithm to correct error. In BCH algorithm, the
primitive polynomial value is GF(2^13) for 512-bytes sector size. And it is
GF(2^14) for 1024-bytes sector size.

This patch will choose correct degree of the remainders (13 or 14) for
different sector size.
Tested in AT91SAM9X5-EK with MLC nand flash.

More detail can be refered to section 5.4.1 of:
  AT91SAM ARM-based Embedded MPU Application Note
  <http://www.atmel.com/Images/doc11127.pdf>

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-09-04 17:07:21 +02:00
Wu, Josh
a07d229497 ARM: at91: atmel_nand: add code to check the ONFI parameter ECC requirement
1. if CONFIG_SYS_NAND_ONFI_DETECTION is defined, driver will check NAND flash's
   ecc minimum requirement in ONFI parameter.

  a) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are defined. then use it.
     Driver will display a WARNING if the values are different from ONFI
     parameters.

  b) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are not defined, then use
      the value from ONFI parameters.
      * If ONFI ECC parameters are in ONFI extended parameter page, since we
        are not support it, so assume the minimum ecc requirement is 2 bits
        in 512 bytes.
      * For non-ONFI support nand flash, also assume the minimum ecc
        requirement is 2 bits in 512 bytes.

2. if CONFIG_SYS_NAND_ONFI_DETECTION is not defined, just use CONFIG_PMECC_CAP
   and CONFIG_PMECC_SECTOR_SIZE.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22 16:50:52 +02:00
Wu, Josh
ddd85974b1 mtd: atmel_nand: alloc memory instead of use static array for pmecc data
In this way, the pmecc corraction capbility can change in run time.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22 16:50:44 +02:00
Wu, Josh
b2d96dc28f ARM: at91: atmel_nand: pmecc driver will select the galois table by sector size
Define the galois index table offset in chip head file. So user do not need
to set by himself. Driver will set it correctly according to sector_size.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
[rebased on master]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22 16:50:16 +02:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Sergey Lapin
dfe64e2c89 mtd: resync with Linux-3.7.1
This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:

- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.

- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).

To produce this update I used tag v3.7.1 of linux-stable repository.

The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.

Signed-off-by: Sergey Lapin <slapin@ossfans.org>
[scottwood@freescale.com: some eccstrength and build fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-05-31 17:12:03 -05:00
Wu, Josh
b9c83c6815 atmel_nand: fix the U-Boot output information about nand flash with PMECC enable.
Before the patch, it looks like:
	|U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:11:06)
	|
	|CPU: AT91SAM9G35
	|Crystal frequency:       12 MHz
	|CPU clock        :      400 MHz
	|Master clock     :  133.333 MHz
	|DRAM:  128 MiB
	|WARNING: Caches not enabled
>	|NAND:  Initialize PMECC params, cap: 2, sector: 512
>	|256 MiB
	|MMC:   mci: 0
	|In:    serial
	|Out:   serial
	|Err:   serial
	|Net:   macb0
	|Hit any key to stop autoboot:  0

After the patch:
	|U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:18:11)
	|
	|CPU: AT91SAM9G35
	|Crystal frequency:       12 MHz
	|CPU clock        :      400 MHz
	|Master clock     :  133.333 MHz
	|DRAM:  128 MiB
	|WARNING: Caches not enabled
>	|NAND:  256 MiB
	|	... ...
	|Hit any key to stop autoboot:  0

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-13 14:28:13 +02:00
Wu, Josh
bdfd59aa0f at91: atmel_nand: Update driver to support Programmable Multibit ECC controller
The Programmable Multibit ECC (PMECC) controller is a programmable binary
BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
can be used to support both SLC and MLC NAND Flash devices. It supports to
generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data.

To use PMECC in this driver, the user needs to set the PMECC correction
capability, the sector size and ROM lookup table offsets in board config file.

This driver is ported from Linux kernel atmel_nand PMECC patch. The main difference
is in this version it uses registers structure access hardware instead of using macros.
It is tested in 9x5 serial boards.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
[rebase]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01 17:06:14 +02:00
Wu, Josh
ae79794e54 at91: atmel_nand: remove unused variables.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01 17:06:14 +02:00
Wu, Josh
fe2185ea80 at91: atmel_nand: extract HWECC initialization code into one function: atmel_hw_nand_init_param().
This patch
1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support.
2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail().

Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix empty newline at EOF error and move return value check into ifdef]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01 17:06:14 +02:00
Stelian Pop
c9e798d35a Fix Stelian's email address
Change my old email address which is no longer valid.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-29 15:43:38 +01:00
michael
67a490d60d atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PIN
If NCE is hooked up to NCS3, we don't need to (and can't)
explicitly set the state of the NCE pin. Instead, the
controller asserts it automatically as part of a
command/data access. Only "CE don't care"-type NAND chips
can be used in this manner.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-04-01 14:49:08 -05:00
Lei Wen
245eb90091 mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()
This patch sync with David's patch on Linux for handling nand_scan_ident.

	commit 5e81e88a4c140586d9212999cea683bcd66a15c6
	Author: David Woodhouse <David.Woodhouse@intel.com>
	Date:   Fri Feb 26 18:32:56 2010 +0000

	mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()

	Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-01-12 17:13:10 -06:00
Nikolay Petukhov
7c27b7b1ea at91: add hwecc method for nand
This is a patch to use the hardware ECC controller of
the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33.

Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>
2010-03-23 14:29:09 -05:00
Jean-Christophe PLAGNIOL-VILLARD
74c076d6c3 at91sam9/at91cap: move nand drivers to drivers/mtd/nand
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-03-22 13:22:24 +01:00
Renamed from board/afeb9260/nand.c (Browse further)