Commit graph

718 commits

Author SHA1 Message Date
Caleb Connolly
2c2cc3e9c0
pinctrl: qcom: make compatible with linux DTs
The pinctrl and GPIO drivers are currently heavily incompatible with
upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at
it's own address. Introduce support for these by allowing the soc driver
to specify per-pin register offsets similarly to the Linux driver.

Adjust the GPIO driver to handle these too, and finally enable support
for all pins with the same numbering as used in Linux.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:52 +00:00
Caleb Connolly
24d2908e98
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx
Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add
it to drivers/pinctrl/qcom.

Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:49 +00:00
Caleb Connolly
53b2c7af69
pinctrl: qcom: move out of mach-snapdragon
Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the
rest of the pinctrl drivers, adjust the drivers so that support for each
platform can be enabled/disabled individually and introduce platform
specific configuration options.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:24 +00:00
Tom Rini
0727b10f6b Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2024-01-09 10:59:29 -05:00
Sam Protsenko
5bf111b77c pinctrl: exynos: Convert to use livetree API for fdt access
Use counterpart dev_read_* functions instead of fdt* ones. It fixes
checkpatch warnings like this:

    WARNING: Use the livetree API (dev_read_...)
    #54: FILE: drivers/pinctrl/exynos/pinctrl-exynos.c:137:
        pinvals[idx] = fdtdec_get_int(fdt, node,

and also makes it possible to avoid using the global data pointer in the
driver.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
da06fefcef pinctrl: exynos: Reduce variables scope
Pull some variables declared in exynos_pinctrl_set_state() into its
loop, to reduce their scope. Style commit, no functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
aad0f6abf1 pinctrl: exynos: Refactor handling the pin related dt properties
All pin related dt properties (pin-function, pin-pud and pin-drv) are
handled in a very similar way. Get rid of that code duplication by
extracting the corresponding data knowledge into an actual data
structure (array), and then just iterating over it.

No functional change, it's a refactoring commit.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
2ed4ba83fb pinctrl: exynos: Support different register types in pin banks
Get rid of hard-coded register offsets and widths. Instead provide a way
for pinctrl drivers to specify different pin bank register offsets and
widths. This in turn makes it possible to add support for new SoCs that
have registers with offset/width values different than generic ones
already available in pinctrl-exynos driver.

Offset constants (now unused in pinctrl-exynos.c) are moved to
pinctrl-exynos7420 driver, which is the single user of those constants.

The design of this patch follows Linux kernel pinctrl-exynos driver
design, in terms of added data structures and types. This patch doesn't
add support for any new SoCs and shouldn't introduce any functional
changes.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
2dfcb250d0 pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name
Rework pin_to_bank_base() function to obtain bank data structure by bank
name instead of getting bank base address by pin name, and rename it to
get_bank() to reflect this change. This in turn leads to the extraction
of parse_pin(), so the caller has to use it before calling get_bank().

No functional change. This is a refactoring commit which prepares
pinctrl driver code for handling different sizes of register fields,
which will be added next.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
58e84bf3d7 pinctrl: exynos: Extract pin parsing code into a separate function
Next commits are going to re-design the pin_to_bank_base() function and
its usage in a way that the pin parsing code will be called separately.
Extract it into a separate function first, as a refactoring commit.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
7b34206e3f pinctrl: exynos: Improve coding style
Style commit, no functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Tom Rini
cb3ce95401 global: Drop common.h inclusion
In order to make it easier to move on to dropping common.h from code
directly, remove common.h inclusion from the rest of the header file
which had been including it.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Svyatoslav Ryhel
b98bed0e9c drivers: pinctrl: tegra: incorporate existing code
Move all existing pinmux and funcmux code into a dedicated folder in
pinctrl to simplify further maintenance.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Svyatoslav Ryhel
91069320a5 drivers: pinctrl: create Tegra DM pinctrl driver
The existing pinctrl driver available for Tegra SOC is well
designed, but it lacks DM support. Let's add a DM compatible
overlay, which allows use of the device tree, along with preserving
backward compatibility with all existing setups and the ability
to use it in SPL board configuration stage.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Tom Rini
dca7a8958f Prepare v2024.01-rc3
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Merge tag 'v2024.01-rc3' into next

Prepare v2024.01-rc3
2023-11-20 09:19:50 -05:00
Patrice Chotard
778f4eaa80 pinctrl: pinctrl_stm32: Add stm32mp2 support
Add stm32mp2 compatible.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Samuel Holland
0070d57c33 pinctrl: sunxi: Avoid using .bss for SPL
sunxi platforms put .bss in DRAM, so .bss is not available in SPL before
DRAM controller initialization. Therefore, this buffer must be placed in
the .data section.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 16:46:46 +00:00
Paul Barker
a1b3787ad3 pinctrl: rzg2l: Drop <common.h>
In line with changes elsewhere, drop inclusion of the common header.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2023-11-02 11:30:18 +01:00
Jim Liu
5572d23f02 pinctrl: npcm8xx: Add name for gpio function
GPIO function name is needed in the debug log

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-10-31 13:07:58 -04:00
Andre Przywara
95168d77d3 sunxi: add Allwinner R528/T113 SoC support
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Andre Przywara
ad9dcb5001 pinctrl: sunxi: add Allwinner D1 pinctrl description
Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:51 +01:00
Andre Przywara
207ed0a3dd pinctrl: sunxi: remove GPIO_EXTRA_HEADER
U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code
to more easily include platform specific GPIO headers. This should not
be needed in a DM world anymore, since the generic GPIO framework
handles that nicely.
For Allwinner boards we still need to deal with non-DM GPIO in the SPL,
but this should become the exception, not the rule.

Make this more obvious by removing the definition of GPIO_EXTRA_HEADER,
and just force every legacy user of platform specific GPIO to include
the new sunxi_gpio.h header explicitly. Everyone doing so should feel
ashamed and should find a way to avoid it from now on.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:57 +01:00
Andre Przywara
30097ee3d2 pinctrl: sunxi: remove struct sunxi_gpio
So far every Allwinner SoC used the same basic pincontroller/GPIO
register frame, and just differed by the number of implemented banks and
pins, plus some special functionality from time to time. However the D1
and successors use a slightly different pinctrl register layout.
Use that opportunity to drop "struct sunxi_gpio", that described that
MMIO frame in a C struct. That approach is somewhat frowned upon in the
Linux world and rarely used there, though still popular with U-Boot.

Switching from a C struct to a "base address plus offset" approach allows
to switch between the two models more dynamically, without reverting to
preprocessor macros and #ifdef's.

Model the pinctrl MMIO register frame in the usual "base address +
offset" way, and replace a hard-to-parse CPP macro with a more readable
static function.
All the users get converted over. There are no functional changes at
this point, it just prepares the stages for the D1 and friends.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:57 +01:00
Paul Barker
21e4ba153f gpio: Add RZ/G2L GPIO driver
This driver adds support for the gpio features of the GPIO/PFC module in
the Renesas RZ/G2L (R9A07G044) SoC.

The new `rzg2l-pfc-gpio` driver is bound to the same device tree node as
the `rzg2l-pfc-pinctrl` driver as the same hardware block provides both
GPIO and pin multiplexing features.

This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 15:46:18 +02:00
Paul Barker
b378c400e0 pinctrl: renesas: Add RZ/G2L PFC driver
This driver adds support for the pinctrl features of the GPIO/PFC module
in the Renesas RZ/G2L (R9A07G044) SoC.

A multi-function `rzg2l-pfc` driver is defined for UCLASS_NOP, which
binds the `rzg2l-pfc-pinctrl` UCLASS_PINCTRL driver dynamically. We also
define common macros and functions for the PFC in <renesas/rzg2l-pfc.h>.
This makes it easy to add an additional UCLASS_GPIO driver for the GPIO
functionality of this module in a follow-up patch.

This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 15:46:18 +02:00
Matthias Schiffer
7f18fb8a27 pinctrl: single: fix compile warnings with PHYS_64BIT on 32bit
pinctrl-single uses fdt_addr_t and phys_addr_t inconsistently, but both
are wrong to be passed to readb() etc., which expect a pointer or
pointer-sized integer. Change the driver to use
dev_read_addr_size_index_ptr(), so we consistently deal with void*
(except for the sandbox case and single_get_pin_muxing()).

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add missing mapmem.h header:
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-10-13 14:01:32 -06:00
Venkatesh Yadav Abbarapu
9898d1056d pinctrl: zynqmp: Display the tristate configuration for all pins
Read the tristate config for all the pins and display it.

ZynqMP> pinmux status MIO1
MIO1: slew:fast	bias:enabled pull:up input:cmos	drive:12mA
      volt:1.8	tri_state:enabled

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230914100620.26346-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-10-09 10:25:32 +02:00
Marek Vasut
bad82145b2 pinctrl: renesas: Synchronize R8A779G0 V4H PFC tables with Linux 6.5.3
Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
d1fd6c7f52 pinctrl: renesas: Synchronize R8A779F0 S4 PFC tables with Linux 6.5.3
Synchronize R-Car R8A779F0 S4 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
c58997112e pinctrl: renesas: Synchronize R8A779A0 V3U PFC tables with Linux 6.5.3
Synchronize R-Car R8A779A0 V3U PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
2cc32389bc pinctrl: renesas: Synchronize R8A77995 D3 PFC tables with Linux 6.5.3
Synchronize R-Car R8A77995 D3 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
a723b2ac32 pinctrl: renesas: Synchronize R8A77990 E3 PFC tables with Linux 6.5.3
Synchronize R-Car R8A77990 E3 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
827cece3aa pinctrl: renesas: Synchronize R8A77980 V3H PFC tables with Linux 6.5.3
Synchronize R-Car R8A77980 V3H PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
b16bd90a12 pinctrl: renesas: Synchronize R8A77970 V3M PFC tables with Linux 6.5.3
Synchronize R-Car R8A77970 V3M PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
617850accd pinctrl: renesas: Synchronize R8A77965 M3-N PFC tables with Linux 6.5.3
Synchronize R-Car R8A77965 M3-N PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
05329b9a00 pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.5.3
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
259aac6a27 pinctrl: renesas: Synchronize R8A77951 H3 PFC tables with Linux 6.5.3
Synchronize R-Car R8A77951 H3 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
84e367c39a pinctrl: renesas: Synchronize R8A7794 E2 PFC tables with Linux 6.5.3
Synchronize R-Car R8A7794 E2 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
49e78ea891 pinctrl: renesas: Synchronize R8A7792 V2H PFC tables with Linux 6.5.3
Synchronize R-Car R8A7792 V2H PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
ef16c759d4 pinctrl: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.5.3
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
7ad92d52c2 pinctrl: renesas: Synchronize R8A7790 H2 PFC tables with Linux 6.5.3
Synchronize R-Car R8A7790 H2 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
f3a163dc86 pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
Currently, the Renesas pin control driver supports pins that can switch
their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V
and 3.3V.  However, some SoCs have pins that can switch between 1.8V and
2.5V.

Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE
capability and voltage level flags by a 2-bit field, to cover three
possible I/O voltage switching options.

Ported from Linux kernel commit by Geert Uytterhoeven:
b88e733ac517 ("pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels")

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
8cf4d3faec pinctrl: renesas: Drop R8A77950 H3 ES1.x PFC table entry
Drop outstanding R8A77950 H3 ES1.x PFC table entry from sh_pfc.h .
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
9f482d7c0e pinctrl: renesas: Rename RZ/A1 R7S72100 PFC tables to RZ/A1
Rename pfc-r7s72100.c to pfc-rza1.c to match the file name with Linux.
Rename the Kconfig symbol to match.

No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Marek Vasut
6db2bb63d2 pinctrl: renesas: Rename R8A7795 H3 PFC tables file name to R8A77951
Rename pfc-r8a7795.c to pfc-r8a77951.c to match the file name with Linux
and to indicate the PFC driver does not support R8A77950 H3 ES1.* .

No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01 00:08:28 +02:00
Simon Glass
1e94b46f73 common: Drop linux/printk.h from common header
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h

Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-24 09:54:57 -04:00
Ashok Reddy Soma
12d2da980e pinctrl: zynqmp: Add support for output-enable and bias-high-impedance
Add support to handle 'output-enable' and 'bias-high-impedance'
configurations in pinctrl driver.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230811054829.13162-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-09-21 13:20:10 +02:00
Ashok Reddy Soma
4af320b10c pinctrl: zynqmp: Add version check for TRISTATE configuration
Support for configuring TRISTATE parameter is added in ZYNQMP PMUFW(Xilinx
ZynqMP Platform Management Firmware) Configuration Param Set version 2.0.
If the requested configuration is TRISTATE then check the version before
requesting Xilinx firmware to set the configuration.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230811054829.13162-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-09-21 13:20:10 +02:00
Jonas Karlman
d7009faa09 pinctrl: rockchip: Fix drive and input schmitt on RK3568
On RK3568 most pins have a configurable drive strength of level 0-5 and
some pins level 0-11. When rk3568_set_drive is called with a strength
value above 7 the drv value written to reg may overflow into the write
enable bits, resulting in a bad configuration.

This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after
drive is configured according to the device tree.

  Could not get PHY for ethernet@fe010000: addr 0

Level 6-11 can be configured using a second reg for some pins, however
the drv value is reused resulting in lower 6 bits being written to reg.

Input schmitt is configured in 2-bit fields on RK3568 compared to
earlier generation and 2'b10 should be used to enable input schmitt.

Change to use regmap_update_bits with a rmask to fix the overflow issue
and closer match the linux driver. Bit shift the drv value used for the
second reg to configure drive strength level 6-11. Also write correct
values for input schmitt setting.

Fixes: 1977d746aa ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-14 11:07:27 +08:00
Weijie Gao
e34cf6fd17 pinctrl: mediatek: add pinctrl driver for MT7988 SoC
This patch adds pinctrl and gpio support for MT7988 SoC

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03 09:40:50 -04:00