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3 commits

Author SHA1 Message Date
Lokesh Vutla
43037d7631 OMAP5: ADD precalculated timings for ddr3 
Adding precalculated timings for ddr3 with 1cs
adding required registers for ddr3

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
 2012-07-07 14:07:23 +02:00
SRICHARAN R
77efdeb758 ARM: OMAP5: dmm: Create a tiler trap section. 
The unmapped entries in tiler space are set with
values 0xFF. So creating a DMM section of
size 16MB at 0xFF000000 with ADDRSPACE set to 0x2.

This way all the unmapped entry accesses to tiler
will be trapped by the EMIF and a error response
is sent to the L3 interconnect. L3 errors are
inturn reported to MPU.

Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
 2012-07-07 14:07:22 +02:00
SRICHARAN R
971f2ba21a OMAP5: ddr: Change the ddr device name. 
The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and
not a ELPIDA part. So change this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
 2012-05-15 08:31:24 +02:00
Renamed from arch/arm/cpu/armv7/omap5/sdram_elpida.c (Browse further)