As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually know what chip select it will appear on.
However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the chip select when the child is bound,
and avoid the messy contortions.
Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.
Signed-off-by: Simon Glass <sjg@chromium.org>
These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
Enable GPMC's prefetch feature for NAND access. This speeds up NAND read
access a lot by pre-fetching contents in the background and reading them
through the FIFO address.
The current implementation has two limitations:
a) it only works in 8-bit mode
b) it only supports read access
Both is easily fixable by someone who has hardware to implement it.
Note that U-Boot code uses non word-aligned buffers to read data into, and
request read lengths that are not multiples of 4, so both partial buffers
(head and tail) have to be addressed.
Tested on AM335x hardware.
Tested-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Guido Martínez <guido@vanguardiasur.com.ar>
Signed-off-by: Daniel Mack <zonque@gmail.com>
[trini: Make apply again, use 'cs' fix pointed out by Guido]
Signed-off-by: Tom Rini <trini@ti.com>
Currently, "nand scrub" runs chip->scan_bbt at the end of
nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set.
It violates the intention of NAND_SKIP_BBTSCAN.
Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that
chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set.
Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt()
right after scrub. We can be lazier here because the BBT is scanned
at the next call of nand_block_checkbad().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Commit 35c204d8a9 (nand: reinstate lazy bad block scanning)
broke NAND_BBT_USE_FLASH feature.
Its git-log claimed that it reinstated the change as by commit
fb49454b1b ("nand: reinstate lazy bad block scanning"), but it moved
"chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);".
It causes recursion if scan_bbt does not find a flash based BBT
and tries to write one, and the attempt to erase the BBT area
causes a bad block check.
Reinstate commit ff49ea8977 (NAND: Mark the BBT as scanned prior to
calling scan_bbt.).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rostislav Lisovy <lisovy@merica.cz>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Since commit ff94bc40af (mtd, ubi, ubifs: resync with Linux-3.14),
the "nand scrub" command has not been working.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
"err" was an unsigned variable, causing negative error codes to turn
into positive values, which are interpreted as an amount of succesfully
corrected bitflips (and thus not an error).
In particular, this resulted in that if the elm reports uncorrectable
errors (-EBADMSG), the MTD layer (and UBI) falsely succeeded.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Stefan Roese <sr@denx.de>
Add the necessary flash entry for the Spansion S25FL164K
flash. Tested on Marvell 88F6218 based design.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Added S25FL116K flash and tested on Marvell 88F6281 based system.
Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add support for SST25WF040B-40I-SN flash.
Tested on T1024QDS board.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Removed ramtron driver since the EMK boards are
no longer been active, and these are the only boards
used this flash driver.
Commit details for EMK zap:
"ppc/arm: zap EMK boards"
(sha1: d58a9451e7)
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.
A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.
Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.
So this fix on sf will correctly handle the slow read supported
controllers.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
'eccstat' array elements might be used uninitialized
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.
Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to detect the NAND chip state. Here the values tested on
Draco with Hynix 4GBit NAND:
Without NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK
time: 2.947 seconds, 2947 ticks
With NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK
time: 2.795 seconds, 2795 ticks
So an increase of approx. 5%.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
This patch disables subpage writes for vf610_nfc nand
driver. This is required, as without this fix, writing
unaligned u-boot images with DFU results in a hang.
Trying to write unalgined binary images also results
in a hang, without disabling subpage writes.
Patch has been tested on a Colibri VF61 module.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Some but not all of implementations of the Denali NAND controller
have hardware circuits to detect the device parameters such as
page_size, erase_size, etc. Even on those SoCs with such hardware
supported, the hardware is known to detect wrong parameters for some
nasty (almost buggy) NAND devices. The device parameters detected
during nand_scan_ident() are more trustworthy.
This commit sets some hardware registers to mtd->pagesize,
mtd->oobsize, etc. in the code between nand_scan_ident() and
nand_scan_tail().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().
CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail(). It is also helpful to reduce
the difference between this driver and its Linux counterpart because
this driver was ported from Linux. Moreover, doc/README.nand recommends
to use CONFIG_SYS_NAND_SELF_INIT.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
Commit ff94bc40af
("mtd, ubi, ubifs: resync with Linux-3.14")
accidentally reverted part of the commit
13f0fd94e3
("NAND: Scan bad blocks lazily.").
Reinstate the change as by commit
fb49454b1b
("nand: reinstate lazy bad block scanning")
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Acked-by: Heiko Schocher <hs@denx.de>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
The SPI function does the same thing, so we may as well just use the new
generic function. The 'cs' parameter was not actually used, so can be
dropped.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
This code was not updated when the chip select handling was adjusted. Fix
it to call the correct function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
The device id makes u-boot think that this chip needs
cfi_reverse_geometry(), which is not the case.
Add it to jedec_flash, so it is handled properly.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
ff94bc40af "mtd, ubi, ubifs: resync with Linux-3.14"
introduced the writebufsize field in struct mtd_info, which
is not initialized in the cfi_flash driver, which leads in
not working ubi on cfi flashes. Fix it
Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
As in SAMA5D4 SoC, the gf table in ROM code can not be seen.
So, when we try to use PMECC, we need to build it when do
initialization.
Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it
is defined we will build gf table runtime.
The PMECC use the BCH algorithm, so based on the build_gf_tables()
function in lib/bch.c, we can build the Galois Field lookup table.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
device ready pin is signalling that the device is ready on state 1
not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
erase one nand block in spl code. keep it simple, as size matters
This is used on the upcoming taurus spl support.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
using this driver in SPL code with CONFIG_SPL_NAND_ECC
configured leads in an compileerror. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add ECC geometry for NAND which has 2048b pagesize and 112b OOB
size. This is for example Macronix MX30LF2G28AB chip.
Signed-off-by: Marek Vasut <marex@denx.de>
- make omap_spl_dev_ready static
- make omap_reverse_list static, move to under CONFIG_NAND_OMAP_ELM
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Tom Rini <trini@ti.com>
For various reasons (design, errata) boards may need to implement their
own versions of these accessors. So in the case of
CONFIG_CFI_FLASH_USE_WEAK_ACCESSOR mark the functions as weak. In the
normal case mark them as static to allow for better optimization.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
[trini: Reword commit message]
Signed-off-by: Tom Rini <trini@ti.com>
This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Convert sandbox's spi flash emulation driver to use driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
We want the SPI flash probing feature to operate as a standard driver.
Add a driver for the basic probing feature used by most boards. This
will be activated by device_probe() as with any other driver.
The 'sf probe' command currently keeps track of the SPI slave that it
last used. This doesn't work with driver model, since some other driver
or system may have probed the device and have access to it too. On the
other hand, if we try to probe a device twice the second probe is a nop
with driver model.
Fix this by searching for the matching device, removing it, and then
probing it again. This should work as expected regardless of other device
activity.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add a driver model uclass for SPI flash which supports the common
operations (read, write, erase). Since we must keep support for the
non-dm interface, some modification of the spi_flash header is required.
CONFIG_DM_SPI_FLASH is used to enable driver model for SPI flash.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Adjust spi_flash_probe_slave() to return an error value instead of a
pointer so we get the correct error return.
Have the caller allocate memory for spi_flash to simplify error handling,
and also so that driver model can use its existing allocated memory.
Add a spi.h include in the sf_params file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Since spi_flash.h is supposed to be the public API for SPI flash, move
private things to sf_internal.h. Also tidy up a few comment nits.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Some files are using SPI functions but not explitly including the SPI
header file. Fix this, since driver model needs it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
The function nand_flash_detect_ext_param_page() requires
NAND_CMD_RNDOUT command supported. It is necessary to detect some
types of ONFi-compliant devices. Without it, the error message
"unsupported command received 0x5" is shown.
Let's support this command on the Denali NAND controller driver.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Chin Liang See <clsee@altera.com>
NAND_CMD_PARAM (0xEC) command is not working on the Denali
NAND controller driver.
Unlike NAND_CMD_READID (0x90), when the NAND_CMD_PARAM command
is followed by an address cycle, the target device goes busy.
(R/B# is deasserted)
Wait until the parameter data are ready.
In addition, unnecessary clear_interrupts() should be removed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Chin Liang See <clsee@altera.com>
Partially revert commit 0d01f66d23 (CFI: cfi_flash write fix for AMD
legacy).
flash_full_status_check() used to skip status register parsing when
flash_status_check() returns OK. This is wrong since flash_status_check()
must return OK for other status bits to be valid.
Cc: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
- CONFIG_SPL_NAND_DENALI
Define to enable this driver.
- CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
Commit 3eb3e72a3f (nand/denali: Adding Denali NAND driver support)
introduced some new options, and some of them were documented by
commit f9860cf081 (nand/denali: Document CONFIG symbols).
This commit allows users to enable/disable them via Kconfig
with more detailed help docs.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
At present sandbox has its own table of supported SPI flash chips. Now that
the SPI flash system is fully consolidated and has its own list, sandbox
should use that.
This enables us to expand the number of chips that sandbox supports.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
To add the Denali NAND driver support into U-Boot.
This driver is leveraged from Linux with commit ID
fdbad98dff8007f2b8bee6698b5d25ebba0471c9. For Denali
controller 64 variance, you need to declare macro
CONFIG_SYS_NAND_DENALI_64BIT.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific
and have been introduced with the Linux MTD v3.14 sync. While introducing
these functions, the length for the loop has been miscalculated. The ">> 1"
is already present in the caller. So lets remove it in the function.
Tested on omap3_ha.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
OMAP GPMC driver used with some NAND Flash devices
(e.g. Spansion S34ML08G1) causes that U-boot shows
hundreds of 'nand: bit-flip corrected' error messages.
Possible cause was discussed in the mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html
The issue was partially fixed with the cc81a5291910d7a.git
however this has to be done to fix the SPL.
The original author of the code is Belisko Marek
<marek.belisko@gmail.com>
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Freescale's flash control driver is using architecture specific timer API
i.e. usec2ticks
Replace usec2ticks with get_timer() (generic timer API)
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Add ID for this Numonix / STMicro chip.
Tested on Marvell DB-78460-BP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
SPL. These #defines do not allow the user to select SPI mode for the SPI flash
(there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
spi_spl_load.c), and duplicate information already provided by
CONFIG_SF_DEFAULT_* #defines.
Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Add support for M25PE16 and M25PX16
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).
Signed-off-by: Simon Glass <sjg@chromium.org>
Disable subpage write when using PMECC to prevent buggy partial page write.
This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access.
But in the driver we also use the readl(b)/writel.
To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
After mtd was synced with Linux 3.14
(ff94bc40af)
the number of parameters for write_page function of nand_chip was
changed. The additional two var were needed for subpage write.
As keystone has no supbage write they are not needed. So correct
only function definition by upgrading it's parameter list.
That helps to get ritd of compilation warning.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
U-Boot has imported various source files from other projects,
mostly Linux.
Something like
#ifdef __UBOOT__
[ modification for U-Boot ]
#else
[ original code ]
#endif
is an often used strategy for clarification of adjusted parts,
that is, easier re-sync in future.
Instead of defining __UBOOT__ in each source file,
passing it from the top Makefile would be easier.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
The driver is called vf610_nfc since this is the first supported
and tested hardware platform supported by the driver.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion
S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip
corrected' error messages. Possible cause was discussed in the
mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html
Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly
due to a NAND protocol violation in the omap driver since the
Random Data Output command (05h-E0h) expects to see only the
column address that should be addressed within the already loaded
read page into the read buffer. Only 2 address cycles with ALE
active should be provided between the 05h and E0h commands. The
Page read command expects the full address footprint (2bytes for
column address + 3bytes for row address), but once the page is
loaded into the read buffer, Random Data Output should be used
with only 2bytes for column address."
This patch combines the solution proposed in the mailinglist and
the patch provided by the Spansion company (GPLv2 code, source:
http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip)
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Since the CS of a device connected to the GPMC was
stored in the global variable, it was not possible to
use multiple devices. In this patch the CS is stored per
device in its 'struct omap_nand_info'. This makes it
possible to use up to 'GPMC_MAX_CS' NAND Flash devices
connected to U-boot.
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
In case when 4K page keystone RBL layout is used the compilation
error is appeared. That's because the #ifdef has to be placed under
struct name. This patch correct it.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Make it configurable to disable subpage writes like the DaVinci NAND
driver already does.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Scott Wood <scottwood@freescale.com>
snyc with linux v3.15:
commit 1860e379875dfe7271c649058aeddffe5afd9d0d
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Jun 8 11:19:54 2014 -0700
Linux 3.15
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
while playing with the new mtd/ubi/ubifs sync, found some
small updates for it:
- add del_mtd_partition() to include/linux/mtd/mtd
- mtd: add a debug_printf
- remove some not used functions
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
resync ubi subsystem with linux:
commit 455c6fdbd219161bd09b1165f11699d6d73de11c
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Mar 30 20:40:15 2014 -0700
Linux 3.14
A nice side effect of this, is we introduce UBI Fastmap support
to U-Boot.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Joerg Krause <jkrause@posteo.de>
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.
The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.
The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.
Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128 thorugh
the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.
Update the page offset calculation logic to support the same.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
IFC controller v1.1.0 requires internal SRAM initialize by reading
NAND flash. Higher controller versions have provided "SRAM init" bit in
NCFGR register space.
update SRAM initialize logic to reflect the same.
Also print error message in case of Page read error.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.
Update MAX_BANKS same as SoC defined
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
clang warns this check is silly; it is since s is
a local variable.
u-boot/drivers/mtd/cfi_flash.c:2363:13: warning: comparison of
array 's' not equal to a null pointer is always true
else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
cc: Stefan Roese <sr@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
The definitions inside emif_defs.h concern davinci nand driver and
should be in it's header. So create header file for davinci nand
driver and move definitions from emif_defs.h and nand_defs.h to it.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[trini: Fixup more davinci breakage]
Signed-off-by: Tom Rini <trini@ti.com>
Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch add support for BCH16_ECC to omap_gpmc driver.
*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)
Signed-off-by: Pekon Gupta <pekon@ti.com>
GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL: SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
which is called before probing for devices, hence any ONFI parameter
information is not available during GPMC initialization.
Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.
This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.
Signed-off-by: Pekon Gupta <pekon@ti.com>
As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.
*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."
*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."
Thus porting following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.
commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
mtd: nand: force NAND_CMD_READID onto 8-bit bus
Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)
The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).
This fixes the column address for a few drivers which imitate the
nand_base defaults.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author: Brian Norris <computersforpeace@gmail.com>
mtd: nand: don't use read_buf for 8-bit ONFI transfers
Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
devices, we need to avoid the upper I/O[16:9] bits. See the following
commit for reference:
commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Date: Thu Dec 5 22:22:04 2013 +0100
mtd: nand: don't use {read,write}_buf for 8-bit transfers
Now, I think that all barriers to probing ONFI on x16 devices are
removed, so remove the check from nand_flash_detect_onfi().
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch
omap-elm.c: replaces -ve integer value returned during errorneous condition,
with proper error-codes.
omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
omap-elm driver to upper layers
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch tries to avoid some local pointer dereferences, by using common
local variables in omap_correct_data_bch()
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch renames 'struct nand_bch_priv' which currently holds private data only
for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
all ECC schemes
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This utilizes existing mxs_nand support layer to provide a method to load an
image off nand for SPL. The flash device will be detected in order to support
multiple flash devices instead of having layout hard coded at build time.
Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.
During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.
Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch introduces a configurable mechanism to disable
subpage writes in the DaVinci NAND driver.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
This mainly converts the am335x_spl_bch driver to the "normal" format
which means a slight change to nand_info within the driver.
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
The commit 6af8dc3ebc broke support for
S25FL032P and S25FL064P by carelessly removing the code handling special
page size for these two SPI NOR flashes and unifying the code under the
assumption that Extended JEDEC ID of 0x4d00 always implies 512b page size.
Add special case handling for these two SPI NOR flashes.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Marek Vasut <marex@denx.de>
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Both of these chips have 256kB big sectors, thus the _256K suffix,
compared to their _64K counterparts, which have 64kB sectors. Also,
they have four times less sectors than their _64K counterparts.
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Prepare for nand spl boot support. It supports nand software ECC and
hardware PMECC.
This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.
This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
omap_elm.h is a generic header used by OMAP ELM driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5
Signed-off-by: Pekon Gupta <pekon@ti.com>
omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5
Signed-off-by: Pekon Gupta <pekon@ti.com>
Each SoC platform (AM33xx, OMAP3, OMAP4, OMAP5) has its own copy of GPMC related
defines and declarations scattered in SoC platform specific header files
like include/asm/arch-xx/cpu.h
However, GPMC hardware remains same across all platforms thus this patch merges
GPMC data scattered across different arch-xx specific header files into single
header file include/asm/arch/omap_gpmc.h
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5
Signed-off-by: Pekon Gupta <pekon@ti.com>
chip->ecc.correct() is used for detecting and correcting bit-flips during read
operations. In omap-nand driver it implemented as:
(a) omap_correct_data(): for h/w based ECC_HAM1 scheme
(b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
for ECC_BCH8 scheme using GPMC and software lib/bch.c
(c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
for ECC_BCH8 scheme using GPMC and ELM
This patch updates (c)
- checks for calc_ecc[]==0x00 so that error_correction is not required for
known good pages.
- adds scalability for other ECC_BCHx scheme by merging following
omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch()
- fixing logic for bit-flip correction based on error_loc[count]
Signed-off-by: Pekon Gupta <pekon@ti.com>
chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by
processing the data passed during Read/Write accesses.
All H/W based ECC schemes use GPMC controller to calculate ECC syndrome.
But each BCHx_ECC scheme has its own implemetation of post-processing and
fetching ECC syndrome from GPMC controller.
This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way:
- merges multiple chip->calculate API for different ECC schemes
omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw()
==> omap_calculate_ecc()
- removes omap_ecc_disable() and instead uses it as inline.
Signed-off-by: Pekon Gupta <pekon@ti.com>
chip->ecc.hwctl() is used for preparing the H/W controller before read/write
NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.)
Though all ECC schemes in OMAP NAND driver use GPMC controller for generating
ECC syndrome (for both Read/Write accesses). But but in current code
HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this.
This patch
(1) removes omap_hwecc_init() and omap_hwecc_init_bch()
as chip->ecc.hwctl will re-initializeGPMC before every read/write call.
omap_hwecc_init_bch() -> omap_enable_ecc_bch()
(2) merges the GPMC configuration code for all ECC schemes into
single omap_enable_hwecc(), thus adding scalability for future ECC schemes.
omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc()
Signed-off-by: Pekon Gupta <pekon@ti.com>
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.
So update acessor functions with common IFC acessor functions to take care
both type of endianness.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc, which is not correct. This leads to
calling chip->ecc.read_subpage which is not a valid
pointer. Therefore clear the flag when switching ecc so
reading in hw mode works again.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Remove the flag SECT_4K for device N25Q128 as the 4K-byte
sub sector erase granularity is available only for top/bottom
8 sectors in some of the N25Q128 chips.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This config will use for defining greater than single flash support.
currently - DUAL_STACKED and DUAL_PARALLEL.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added macronix flash quad read/write commands support and
it's up to the respective controller driver usecase to
configure the respective commands by defining SPI RX/TX
operation modes from include/spi.h on the driver.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch adds set QEB support for macronix flash devices
which are trying to program/read quad operations.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Moved the flash params table from sf_probe.c and
placed on to sf_params.c, hence flash params file will
alter based on new addons.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch enabled RD_FULL and WR_QPP for supported flashes
in micron, winbond and spansion.
Remaining parts will be add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch provides support to set the quad enable bit on flash.
quad enable bit needs to set before performing any quad IO
operations on respective SPI flashes.
Currently added set quad enable bit for winbond and spansion flash
devices. stmicro flash doesn't require to set as qeb is volatile.
remaining flash devices support will add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch provides support to program a flash config register.
Configuration register contains the control bits used to configure
the different configurations and security features of a device.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch add quad commands support like
- QUAD_PAGE_PROGRAM => for write program
- QUAD_OUTPUT_FAST ->> for read program
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Current sf uses FAST_READ command, this patch adds support to
use the different/extended read command.
This implementation will determine the fastest command by taking
the supported commands from the flash and the controller, controller
is always been a priority.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Fix unaligned access in OneNAND core. The problem is that the ffchars[] array
is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed
to the memcpy_16() function. The memcpy_16() function will treat the buffer as
an array of "unsigned short", thus triggering unaligned access if the compiler
decided ffchars[] to be not aligned.
I managed to trigger the problem with regular ELDK 5.4 GCC compiler.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Add support for Macronix MX25L2006E SPI flash.
Signed-off-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
All other hex values in sf_probe.c are in lower case so we should
fix this one too.
Signed-off-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
If we change to software ecc and then back to hardware ecc, the nand ecc ops
pointers are populated with incorrect function pointers. This is related to the
way nand_scan_tail() handles assigning functions to ecc ops:
If we are switching to software ecc/no ecc, it assigns default functions to the
ecc ops pointers unconditionally, but if we are switching to hardware ecc,
the default hardware ecc functions are assigned to ops pointers only if these
pointers are NULL (so that drivers could set their own functions). In the case
of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are
assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc,
the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite
them with hw ecc functions.
The result: sw ecc functions used to write hw ecc data.
Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that
ops which were not assigned by the driver will get the correct default values
from nand_scan_tail().
Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values
into the current nand chip's ecc.layout struct. This is done under the
assumption that the struct exists only to store values, so it is OK to overwrite
it, but there is at least one situation where this assumption is incorrect:
When switching to 1 bit hamming code sw ecc, the job of assigning layout data
is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a
pointer to an existing struct prefilled with the appropriate values. This struct
doubles as both data and layout definition, and therefore shouldn't be
overwritten, but on the next switch to hardware ecc, this is exactly what's
going to happen. The next time the user switches to software ecc, they're
going to get a messed up ecc layout.
Prevent this and possible similar bugs by explicitly using the
private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic
platform" (d016dc42ce) changed the way
software ECC is configured, both during boot, and during ecc switch, in a way
that is not backwards compatible with older systems:
Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring
for software ecc, relying on nand_scan_tail() to select a default for ecc.size
(256), while the new version of omap_gpmc.c assigns ecc.size = pagesize,
which is likely to not be 256.
Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert
to the original behavior.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Pekon Gupta <pekon@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: wrap some long lines]
Signed-off-by: Scott Wood <scottwood@freescale.com>
As per OMAP3530 TRM referenced below [1]
For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
- OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
- OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device
Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
*for x8 NAND Device*
+--------+---------+---------+---------+---------+---------+---------+
| xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
+--------+---------+---------+---------+---------+---------+---------+
*for x16 NAND Device*
+--------+--------+---------+---------+---------+---------+---------+---------+
| xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] |
+--------+--------+---------+---------+---------+---------+---------+---------+
This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.
[1] OMAP3530: http://www.ti.com/product/omap3530
TRM: http://www.ti.com/litv/pdf/spruf98x
Chapter-25: Initialization Sub-topic: Memory Booting
Section: 25.4.7.4 NAND
Figure 25-19. ECC Locations in NAND Spare Areas
Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Stefan Roese <sr@denx.de>
This adds a SPI flash driver which simulates SPI flash clients.
Currently supports the bare min that U-Boot requires: you can
probe, read, erase, and write. Should be easy to extend to make
it behave more exactly like a real SPI flash, but this is good
enough to merge now.
sjg@chromium.org added a README and tidied up code a little.
Added a required map_sysmem() for sandbox.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Existing eSPI SPL framework assumes booting from spi-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.
So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.
Signed-off-by: York Sun <yorksun@freescale.com>
This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed
CONFIG_xx used for selecting NAND ecc-schemes.
This patch aims at solving following issues.
1) Currently ecc-scheme is tied to SoC platform, which prevents user to select
other ecc-schemes also supported in hardware. like;
- most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite
the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with
software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW).
- most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware
supports BCH16 ecc-scheme also.
2) Different platforms use different CONFIG_xx to select ecc-schemes, which
adds confusion for user while migrating platforms.
- *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only
8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW)
whereas ELM hardware engine supports other ecc-schemes also like; BCH4,
and BCH16 (in future).
- *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error
correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW).
- *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library
Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency
on SoC platform and NAND driver. And user can select ecc-scheme independently
foreach board.
However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still
depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand)
Signed-off-by: Pekon Gupta <pekon@ti.com>
BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours
+-----------------------------------+-----------------+-----------------+
|ECC Scheme | ECC Calculation | Error Detection |
+-----------------------------------+-----------------+-----------------+
|OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine |
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library |
+-----------------------------------+-----------------+-----------------+
Current implementation limits the BCH8_CODE_HW only for AM33xx device family.
(using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have
ELM hardware module, and can support ECC error detection using ELM.
This patch
- removes CONFIG_AM33xx
Thus this driver can be reused by all devices having ELM h/w engine.
- adds omap_select_ecc_scheme()
A common function to handle ecc-scheme related configurations. This
can be used both during device-probe and via user-space u-boot commads
to change ecc-scheme. During device probe ecc-scheme is selected based
on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8
- enables CONFIG_BCH
S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW
is enabled by CONFIG_BCH.
- enables CONFIG_SYS_NAND_ONFI_DETECTION
for auto-detection of ONFI compliant NAND devices
- updates following README doc
doc/README.nand
board/ti/am335x/README
doc/README.omap3
Signed-off-by: Pekon Gupta <pekon@ti.com>
[scottwood@freescale.com: fixed unused variable warning]
Signed-off-by: Scott Wood <scottwood@freescale.com>
ELM hardware engine which is used for ECC error detection, is present on all
latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM
driver should be moved to common drivers/mtd/nand/ folder so that all SoC
having on-chip ELM hardware engine can re-use it.
This patch has following changes:
- mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h
- mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c
- update Makefiles
- update #include <asm/elm.h>
- add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c
and include in all board configs using AM33xx SoC platform.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Current IFC driver supports till 4K page size NAND flash.
Add support of 8K NAND flash
- Program Spare region size in csor_ext
- Add nand_ecclayout for 4 bit & 8 bit ecc
- Defines constants
- Add support of 8K NAND boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Liu Po <po.liu@freescale.com>
nand_ecclayout is present in mtd.h at Linux.
Move this structure to mtd.h to comply with Linux.
Also, increase the ecc placement locations to 640 to suport device having
writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone
up to 640 bytes and consequently the maximum ecc placement locations have
also gone up to 640.
Changes from Prabhabkar's version (squashed into one patch to preserve
bisectability):
- Added _LARGE to MTD_MAX_*_ENTRIES
This makes the names match current Linux source, and resolves
a conflict between
http://patchwork.ozlabs.org/patch/280488/
and
http://patchwork.ozlabs.org/patch/284513/
The former was posted first and is closer to matching Linux, but
unlike Linux it does not add _LARGE to the names. The second adds
_LARGE to one of the names, and depends on it in a subsequent patch
(http://patchwork.ozlabs.org/patch/284512/).
- Made max oobfree/eccpos configurable, and used this on tricorder,
alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build
for me without doing so, due to a size increase).
On tricorder SPL, this saves 2576 bytes (and makes the SPL build
again) versus the new default of 640 eccpos and 32 oobfree, and
saves 336 bytes versus the old default of 128 eccpos and 8 oobfree.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Vipin Kumar <vipin.kumar@st.com>
[scottwood@freescale.com: changes as described above]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
as per controller description,
"While programming a NAND flash, status read should never skipped.
Because it may happen that a new command is issued to the NAND Flash,
even when the device has not yet finished processing the previous request.
This may result in unpredictable behaviour."
IFC controller never polls for R/B signal after command send. It just return
control to software. This behaviour may not occur with NAND flash access.
because new commands are sent after polling R/B signal. But it may happen
in scenario where GPCM-ASIC and NAND flash device are working simultaneously.
Update the controller driver to take care of this requirement
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
board/compulab/cm_t35/Makefile
board/corscience/tricorder/Makefile
board/ppcag/bg0900/Makefile
drivers/bootcount/Makefile
include/configs/omap4_common.h
include/configs/pdnb3.h
Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:
board/compulab/common/Makefile
board/udoo/Makefile
include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.
include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.
Note: 'git show' will also list two files just because
they are new:
include/configs/am335x_igep0033.h
include/configs/omap3_igep00x0.h
enable the RBL/UBL ECC layout through
CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC define
see for more info:
http://processors.wiki.ti.com/index.php/DM365_Nand_ECC_layout
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Prior to SPDX licensing this file was GPL-2.0 with Freescale granting
rights for "or later" for their contributed code. We incorrectly moved
this file to GPL-2.0+, so correct it to GPL-2.0. In addition we cannot
easily denote in the file where or what code is "or later", so just set
that aside for now and the file as a whole is GPL-2.0 regardless.
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
NAND_ECC_SOFT was the only option available while the SOFT_BCH option
may also be used.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Scott Wood <scottwood@freescale.com>
As the spi flash transfer to multiple parts, it is forgot to add
Atmel AT25DF321 spi flash support, which broken several Atmel EK
boards which this chip. So, add it
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Added GPL-2.0+ SPDX-License-Identifier for missed sf
source files.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Linux modified the MTD driver interface in commit edbc4540 (with the
same name as this commit). The effect is that calls to mtd_read will
not return -EUCLEAN if the number of ECC-corrected bit errors is below
a certain threshold, which defaults to the strength of the ECC. This
allows -EUCLEAN to stop indicating "some bits were corrected" and begin
indicating "a large number of bits were corrected, the data held in
this region of flash may be lost soon". UBI makes use of this and when
-EUCLEAN is returned from mtd_read it will move data to another block
of flash. Without adopting this interface change UBI on U-boot attempts
to move data between blocks every time a single bit is corrected using
the ECC, which is a very common occurance on some devices.
For some devices where bit errors are common enough, UBI can get stuck
constantly moving data around because each block it attempts to use has
a single bit error. This condition is hit when wear_leveling_worker
attempts to move data from one PEB to another in response to an
-EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is
called to perform the data copy, and after the data is written it is
read back to check its validity. If that read returns UBI_IO_BITFLIPS
(in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to
wear_leveling worker, which then proceeds to schedule the destination
PEB for erasure. This leads to erase_worker running on the PEB, and
following a successful erase wear_leveling_worker is called which
begins this whole cycle all over again. The end result is that (without
UBI debug output enabled) the boot appears to simply hang whilst in
reality U-boot busily works away at destroying a block of the NAND
flash. Debug output from this situation:
UBI DBG: ensure_wear_leveling: schedule scrubbing
UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027
UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096
UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083
UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data
UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192
UBI: fixable bit-flip detected at PEB 1027
UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096
UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083
UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192
UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192
UBI: fixable bit-flip detected at PEB 4083
UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0
UBI DBG: erase_worker: erase PEB 4083 EC 55
UBI DBG: sync_erase: erase PEB 4083, old EC 55
UBI DBG: do_sync_erase: erase PEB 4083
UBI DBG: sync_erase: erased PEB 4083, new EC 56
UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0
UBI DBG: ensure_wear_leveling: schedule scrubbing
UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
...
This patch adopts the interface change as in Linux commit edbc4540 in
order to avoid such situations. Given that none of the drivers under
drivers/mtd return -EUCLEAN, this should only affect those using
software ECC. I have tested that it works on a board which is
currently out of tree, but which I hope to be able to begin
upstreaming soon.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
There is no page_size for ramtron flashes,
so just print the detected flash and it's size.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.
This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of "memory_map" flag.
- Add support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Use flash->page_size arg in print_size() instead of
flash->sector_size while printing detected flas part details.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Now the common probing is handled in spi_flash_probe.c
hence removed the unneeded flash drivers.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Compared to other spi flashes, ramtron has a different
probing and implementation on flash ops, hence moved
ramtron probe code into ramtron driver.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
From Micron, 512MB onwards, flash requires to poll flag status
instead of read status- hence added E_FSR flag on spectific
flash parts.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
SECT_4K, SECT_32K and SECT_64K opeartions are performed to
to specific flash by adding a SECT* flag on respective
spi_flash_params.flag param.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Few of the flashes(Atmel, Macronix and SST) require to
clear BP# bits in flash power ups.
So clear these BP# bits at probe time, so-that the flash
is ready for user operations.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Most of the SST flashes needs to write up using SST_WP, AAI
Word Program, so added a flag param on spi_flash_params table.
SST flashes, which supports SST_WP need to use a WP write
sst_write_wp instead of common flash write.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added AT45DB* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added SST25* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Added S25FL* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added W25* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added MX25L* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added GD25* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added EN25Q* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added M25P* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added new spi_flash_probe support, currently added N25Q*
flash part attributes support.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Divided the spi_flash framework into mutiple parts for
- spi_flash.c:
spi flash core file, interaction for spi/qspi driver to
spi_flash framework.
- spi_flash_ops.c
spi flash preffered operations, erase,write and read.
- spi_flash_probe.c
spi flash probing, easy to extend probing functionality.
This change will support to extend the functionality in a
proper manner.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
On a board with an i.mx28 and a Micron MT29F4G08ABAEAH4, Linux says:
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron MT29F4G08ABAEAH4),
512MiB, page size: 4096, OOB size: 224) the ECC strength is 16.
root@(none):/sys/devices/virtual/mtd/mtd0# for i in ecc_strength oobsize subpagesize; do echo $i = `cat $i`; done
ecc_strength = 16
oobsize = 224
subpagesize = 4096
The ECC strength was not properly discovered by U-Boot causing the data
written by Linux to return an -74 (EBADMSG) when read from U-Boot. This
patch fixes mxs_nand_get_ecc_strength() to function in case of a NAND
flash with page_data_size = 4096 and page_oob_size= 224.
Signed-off-by: Elie De Brauwer <eliedebrauwer@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
The PMECC use BCH algorithm to correct error. In BCH algorithm, the
primitive polynomial value is GF(2^13) for 512-bytes sector size. And it is
GF(2^14) for 1024-bytes sector size.
This patch will choose correct degree of the remainders (13 or 14) for
different sector size.
Tested in AT91SAM9X5-EK with MLC nand flash.
More detail can be refered to section 5.4.1 of:
AT91SAM ARM-based Embedded MPU Application Note
<http://www.atmel.com/Images/doc11127.pdf>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
1. if CONFIG_SYS_NAND_ONFI_DETECTION is defined, driver will check NAND flash's
ecc minimum requirement in ONFI parameter.
a) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are defined. then use it.
Driver will display a WARNING if the values are different from ONFI
parameters.
b) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are not defined, then use
the value from ONFI parameters.
* If ONFI ECC parameters are in ONFI extended parameter page, since we
are not support it, so assume the minimum ecc requirement is 2 bits
in 512 bytes.
* For non-ONFI support nand flash, also assume the minimum ecc
requirement is 2 bits in 512 bytes.
2. if CONFIG_SYS_NAND_ONFI_DETECTION is not defined, just use CONFIG_PMECC_CAP
and CONFIG_PMECC_SECTOR_SIZE.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
In this way, the pmecc corraction capbility can change in run time.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Define the galois index table offset in chip head file. So user do not need
to set by himself. Driver will set it correctly according to sector_size.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
[rebased on master]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This patch cleans up license header in these files:
board/freescale/p1022ds/spl.c
drivers/mmc/fsl_esdhc_spl.c
drivers/mtd/spi/fsl_espi_spl.c
Signed-off-by: York Sun <yorksun@freescale.com>
TPL is introduced in the patch "NAND: TPL : introduce the TPL
based on the SPL", here enable TPL for p1022ds nand boot.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
This patch introduces SPL to enable a loader stub that being loaded by
the code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.
The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
ddr spd code can get the interleaving mode setting in env. It loads
final uboot image from offset 96KB.
* final uboot image, size is variable depends on the functions enabled.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Add support for SST25WF080 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
- line over 80 characters
- foo * bar -> foo *bar
- removed unnecessary for single statement blocks.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
While the flash_detect_legacy() of drivers/mtd/cfi_flash.c
feed unmap_physmem() with MAP_NOCACHE as 2nd parameter,
the do_spi_flash_read_write() of common/cmd_sf.c
feed unmap_physmem() with the length of the mapped buffer
as 2nd parameter.
It's apparently a bug, and I personally think the 2nd parameter
should be the length of the mapped buffer.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The driver triggered a BUG() in nand_base.c:3214/nand_scan_tail()
because the ecc.strength was not set in NAND_ECC_HW_SYNDROME ECC
mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Newer gcc versions warn about unused variables. This patch corrects a few of
those warnings that popped up in a build for the palmtreo680 board.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
before writing the received buffer to nand, erase the nand
sectors. If not doing this, nand write fails. See for
more info here:
http://lists.denx.de/pipermail/u-boot/2013-June/156361.html
Using the nand erase option "spread", maybe overwrite
blocks on, for example another mtd partition, if the
erasing range contains bad blocks.
So a limit option is added to nand_erase_opts()
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Move common flash write code into spi_flash_write_common().
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)
With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.
As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use the exact names for W25Q 0x40XX ID's flash parts, as the same
sizes of flashes comes with different ID's. so-that the distinguishes
becomes easy with this change.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Corrected the name of S25FL128S 64K sector part SPI flash,
S25FL128S supported has been added in below commit
"sf: spansion: Add support for S25FL128S"
(sha1: 1bfb9f156a)
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds
common/Makefile: Avoid compiling unnecssary files
fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit dfe64e2c89
Author: Sergey Lapin <slapin@ossfans.org>
Date: Mon Jan 14 03:46:50 2013 +0000
mtd: resync with Linux-3.7.1
changed the initialization of BBT options. Fix drivers
jz4740 and s3c2410 which have not been updated yet and
cause compile errors.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Commit dfe64e2c89:
mtd: resync with Linux-3.7.1
broke the docg4 driver. Specifically:
- some of the prototypes of the ecc methods changed
- the NAND_NO_AUTOINCR flag was removed
- the ecc.strength element was added.
This patch fixes these. Tested on the docg4 on my palmtre680 board.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
This patch corrected the nr_blocks used for W25Q32DW SPI flash.
nr_blcoks are incorrectly assigned on below patch
"sf: winbond: add W25Q32DW"
(sha1: 772ba15474)
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Add support for Winbond W25Q80BW SPI flash.
This patch corrected the flash name, nr_blocks and
also commit message header from below patch.
"sf: winbond: add W25Q32"
(sha1: c969abc470)
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
As the per the ID tabl the flash is under Uniform 64-kB sector
architecture, hence updated with proper name.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch adds a print messages while using 'sf read' and
'sf write' commands to make sure that how many bytes read/written
from/into flash device.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Tom Rini <trini@ti.com>
This patch adds a print messages while using 'sf erase' command
to make sure that how many bytes erased in flash device.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Tom Rini <trini@ti.com>
Missing return after memcpy is done for memory-mapped SPI flashes,
hence added retun 0 after memcpy done.
The return is missing in below patch
"sf: Enable FDT-based configuration and memory mapping"
(sha1: bb8215f437)
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:
- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.
- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).
To produce this update I used tag v3.7.1 of linux-stable repository.
The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
[scottwood@freescale.com: some eccstrength and build fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Add support for Winbond's W25PXX SPI flash.
These devices is used on Faraday A369 evaluation board.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
CC: Tom Rini <trini@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add support for Winbond W25Q256 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This is a S25FL064A successor. It supports up to 104MHz bus
speed.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When base address given was out of valid flash address ranges,
flash_get_info() function returned the pointer to the last
element of flash_info[i] array.
This patch changes this function to return NULL pointer
in such a case, which is more correct behaviour.
The function flash_protect_default() calls flash_protect()
immediately after flash_get_info() invocation.
With this correction, flash_protect() function would be
able to return soon, for NULL flash_info.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Linux Kernel Documentation/CodingStyle says:
Do not add a space after unary operators such as &, *, ...
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Packed structure cfi_qry contains unaligned 16- and 32-bits members,
accessing which causes problems when cfi_flash driver is compiled with
-munaligned-access option: flash initialization hangs, probably
due to data error.
Since the structure is supposed to replicate the actual data layout
in CFI Flash chips, the alignment issue can't be fixed in the structure.
So, unaligned fields need using of explicit unaligned access macros.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Stefan Roese <sr@denx.de>
When a all 0xFF buffer is passed to drop_ffs, the no-0xFF check loop
will loop forever.
After the fix, If ssize_t i = -1 and size_t l = i + 1, the value of l
will still be 0 as expected.
Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Scott Wood <scottwood@freescale.com>
When writelen is mtd->writesize - 1, it is still a partial page write
Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
This avoids needing a separate U-Boot config when some revisions
of a board have small-page NAND and other revisions have large-page
NAND (except for NAND SPL targets).
CONFIG_FSL_ELBC_FMR is removed -- it was never used nor documented, and
it gets in the way of this change.
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds driver for the gigabyte devices
GD25LQ and GD25Q64B required for Snow Board.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The manual resolution in commit ec7023db wrongly removed functions
nand_init and nand_deselect from file drivers/mtd/nand/mxc_nand_spl.c.
Revert this removal.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch adds a driver for the diskonchip G4 nand flash device. It is based
on the driver from the linux kernel.
This also includes a separate SPL driver. A separate SPL driver is used because
the device operates in a different mode (reliable mode) when loading a boot
image, and also because the storage format of the boot image is different from
normal data (pages are stored redundantly). The SPL driver basically mimics how
a typical IPL reads data from the device. The special operating mode and
storage format are used to compensate for the fact that the IPL does not contain
the BCH ecc decoding algorithm (due to size constraints). Although the u-boot
SPL *could* use ecc, it operates like an IPL for the sake of simplicity and
uniformity, since the IPL and SPL share the task of loading the u-boot image.
As a side benefit, the SPL driver is very small.
[port from linux kernel 3.4 commit 570469f3bde7f71cc1ece07a18d54a05b6a8775d]
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Add support for generic NAND SPL via the SPL framework into the
mxc_nand_spl driver. This is basically just a simple rename and
publication of the already implemented functions. To avoid the
bare-bones functions getting in the way of the NAND_SPL, build
them only if CONFIG_SPL_FRAMEWORK is not defined.
Also make sure the requested payload is aligned to full pages,
otherwise this simple driver fails to load the last page.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Delete all occurrences of hang() and provide a generic function.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <trini@ti.com>
The following headers are moved to a i.MX common location:
- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.h
This way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of
the 1-bit error correction code on the NAND device.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so
remove associated code. It will still be possible to restore it later from the
Git history if necessary.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fa.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
The syndrome functions should use the page number passed as argument instead of
the page number saved upon NAND_CMD_READ0.
This does not make any difference if the NAND_NO_AUTOINCR option is set, but
otherwise this fixes accesses to the wrong pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did
not match the page being worked on.
By the way, replace the GCC-specific __FUNCTION__ with __func__.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Add some abstraction to NFC definitions so that some parts of the current code
can also be used for future i.MX5 code.
Clean up a few things by the way.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Currently is_16bit_nand() is a per SoC function and it decides the bus nand
width by reading some boot related registers.
This method works when NAND is the boot medium, but does not work if another
boot medium is used. For example: booting from a SD card and then using NAND
to store the environment variables, would lead to the following error:
NAND bus width 16 instead 8 bit
No NAND device found!!!
0 MiB
Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width.
If it is defined in the board file, then consider 16-bit NAND bus-width,
otherwise assume 8-bit NAND is used.
This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which
states:
nand-bus-width : 8 or 16 bus width if not present 8
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller
drivers could use it when a 16-bit NAND is deployed.
drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that
other NAND drivers could reuse the same symbol.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
The unwind code was not reversing operations correctly and was causing
a hang on any error condition.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
We make these two functions take a size_t pointer to how much space
was used on NAND to read or write the buffer (when reads/writes happen)
so that bad blocks can be accounted for. We also make them take an
loff_t limit on how much data can be read or written. This means that
we can now catch the case of when writing to a partition would exceed
the partition size due to bad blocks. To do this we also need to make
check_skip_len count not just complete blocks used but partial ones as
well. All callers of nand_(read|write)_skip_bad are adjusted to call
these with the most sensible limits available.
The changes were started by Pantelis and finished by Tom.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Tom Rini <trini@ti.com>
The kernel states:
---8<---
The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not
provide automatic error location and correction: this step is implemented using
the BCH library.
--->8---
And we do so in u-boot.
This implementation uses the same layout for BCH8 but it is fix. The current
provided layout does only work with 64 Byte OOB.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Mansoor Ahamed <mansoor.ahamed@ti.com>
Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
With uppcoming BCH support on OMAP devices we need to decide between differnt
algorithms when switching the ECC engine. Currently we support 1-bit hammign
and 8-bit BCH on HW backend.
In order to switch between differnet ECC algorithms we need to change the
interface of omap_nand_switch_ecc() also.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and
arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate
the common parts into a new header.
Introduce a new asm/omap_gpmc.h which defines the command part and pulls in
the architecture specific one.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
This fixes this build warning:
Configuring for qemu_mips64 - Board: qemu-mips64, Options: SYS_BIG_ENDIAN
text data bss dec hex filename
215344 13082 218720 447146 6d2aa qemu_mips64/u-boot
cfi_flash.c: In function 'flash_map':
cfi_flash.c:217:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
This patch addjusted the write buffer size for M29EW devices those
are operated in 8-bit mode.
The M29EW devices seem to report the CFI information wrong when
it's in 8 bit mode.
There's an app note from Numonyx on this issue and there's a patch
in the open source as well for Linux, but it doesn't seem to be in mainline.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This commit is based on that patch from aaron.williams@caviumnetworks.com
with same commit title. pulled the same code changes into current u-boot tree.
http://patchwork.ozlabs.org/patch/140863/http://lists.denx.de/pipermail/u-boot/2011-April/089606.html
This patch corrects the addresses used when working with Spansion/AMD FLASH chips.
Addressing for 8 and 16 bits is almost identical except in the 16-bit case the
LSB of the address is always 0. The confusion arose because the addresses
in the datasheet for 16-bit mode are word addresses but this code assumed it was
byte addresses.
I have only been able to test this on our Octeon boards which use either an 8-bit
or 16-bit bus. I have not tested the case where there's an 8-bit part on a 16-bit
bus.
This patch also adds some delays as suggested by Spansion.
If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an
8-bit bus is detected.
Apart from the pulled changes, fixed few minor code cleanups and tested
on 256M29EW, 512M29EW flashes.
Before this fix:
---------------
Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF
Erase timeout: 4096 ms, write timeout: 2 ms
Buffer write timeout: 5 ms, buffer size: 1024 bytes
After this fix:
--------------
Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301
Erase timeout: 4096 ms, write timeout: 2 ms
Buffer write timeout: 5 ms, buffer size: 1024 bytes
Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.
Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: York Sun <yorksun@freescale.com>
Add support for Winbond W25Q32DW 32Mbit part
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
- In arch/arm/cpu/armv7/omap-common/timer.c,
drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
<asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
as that is the only include which defines things the config uses.
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
Enable device tree control of SPI flash, and use this to implement
memory-mapped SPI flash, which is supported on Intel chips.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of
bytes that can be in a write transaction. Support this by breaking the
writes into multiple transactions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than each device having its own way to allocate a SPI flash
structure, use the new allocation function everywhere. This will make it
easier to extend the interface without breaking devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present it is difficult to extend the SPI flash structure since
all devices allocate it themselves, and few of them zero all fields.
Add a new function spi_flash_alloc() which can be used by SPI devices
to perform this allocation, and thus ensure that all devices can
better cope with SPI structure changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these
conflicts manually and comment the #else/#endif lines for clarity.
Conflicts:
arch/arm/include/asm/arch-davinci/gpio.h
drivers/gpio/da8xx_gpio.c
Signed-off-by: Tom Rini <trini@ti.com>
Tested with an IGEPv2 board seems that current onenand_spl_load_image implementation
doesn't work. This patch fixes this function changing the read loop and reading the
onenand blocks from page to page.
Tested with various IGEP based boards with a OneNAND from Numonyx.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
If the NAND is locked tight, commands such as lock and unlock will not
work, but the NAND chip may not report an error. Check the lock tight
status before attempting such operations so that an error status can be
reported if we know the operation will not succeed.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
If CONFIG_NAND_ECC_BCH is set we use 4-bit error corretion code
instead of the 1-bit error correction code on the NAND device
within this driver.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Add support for Numonyx N25Q256A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for Numonyx N25Q32A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for Numonyx N25Q32 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for Numonyx N25Q64A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for Winbond's W25Q64W SPI flash.
This device is used on xilinx zynq emulation platform.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch corrected the first byte of idcode1 for S25FL256S SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Not only Spansion supports the Persistent Protection Bits (PPB) locking.
Other devices like the Micron JS28F512M29EWx also support this type
of locking/unlocking. Detection of support is done in the same way as
done for the Spansion chips - via the 0x49 CFI word.
This patch enables this PPB protection mechanism for all AMD type
(AMD commandset) chips.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
Patch 66863b05 [cfi_flash: add support for Spansion flash PPB sector
protection] introduced the PPB (Persistent Protection Bit) locking for
Spansion chips. But right now the sector protection status (locked vs
unlocked) is set to unlocked for all sectors upon bootup. The real
sector protection status is ignored.
This patch now reads the current sector protection status and uses
it for these AMD/Spansion flash chips.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
Consolidate manufacturer matching into the function manufact_match()
and use it.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
Add support for SST 4KB sector granularity.
Many recent SST flashes, i.e. SST39VF3201B and similar of this family
are declared CFI-conformant from SST. They support CFI query, but implement
2 different sector sizes in the same memory: a 64KB sector (they call it
"block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector",
erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh
of cfi query struct, detects a number of secotrs for the 4KB granularity
(flinfo shows it).
For all other aspects, they are CFI compliant, so, as Linux do, i think
it's a good idea to handle these chips in the CFI driver, with a fixup
to allow 4KB granularity, as should be expected, instead of 64KB.
Signed-off-by: Angelo Dureghello <sysamfw@gmail.com>
Signed-off-by: Stefan Rose <sr@denx.de>
IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.
NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com>
It could happen (1 out of 100 times) that NAND did not start up correctly after
warm rebooting, so we end up with various failures or DMA timed out due to a
stalled BCH. When resetting BCH together with GPMI, the issue could not be
observed anymore (after 10000+ reboots). We probably need the consistent state
already before sending commands to NAND. This behaviour was observed in barebox
and kernel, so I assume it affects U-Boot as well. I chose to keep the extra
reset for BCH when changing the flash layout to be on the safe side.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
AM33XX with BCH8 can't work with nand_spl_simple correctly
because custom read_page implementation is required for proper
syndrome generation.
This simple driver mostly duplicates nand_spl_simple but has
nand_read_page changed to suit our needs.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This patch adds support for BCH8 error correction code to omap_gpmc
driver. We use GPMC to generate codes/syndromes but we need ELM to find
error locations from given syndrome.
Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
[ilya: merge it with omap_gpmc driver, some fixes and cleanup]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.
This code is ported from mtd-utils' lib/libmtd.c.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND Flash is erased by blocks, not by pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
This patch cleans up nand_util.c:
- Fix tabs.
- Fix typos.
- Remove space character before opening parenthesis in function calls.
- Fix comments.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).
This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.
Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[scottwood@freescale.com: fix fsl_ifc_sram_init prototype]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Document parameters used for specifying the NAND image to be loaded.
Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only
nand_spl_simple.c, not the entire nand directory. The word "simple" is
there for a reason. :-)
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: updated for makefile changes earlier in patchset
Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
nand_ecc.c:82:5: warning: symbol 'nand_calculate_ecc' was not declared. Should it be static?
nand_ecc.c:155:5: warning: symbol 'nand_correct_data' was not declared. Should it be static?
nand_base.c:2854:1: error: directive in argument list
nand_base.c:2856:1: error: directive in argument list
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
cfi_flash.c:756:43: warning: Using plain integer as NULL pointer
cfi_flash.c:1150:52: warning: cast to non-scalar
cfi_flash.c:1433:46: warning: cast truncates bits from constant value (890089 becomes 89)
cfi_flash.c:1490:61: warning: cast truncates bits from constant value (1f001f becomes 1f)
cfi_flash.c:1508:61: warning: cast truncates bits from constant value (10001 becomes 1)
cfi_flash.c:1738:63: warning: cast truncates bits from constant value (10001 becomes 1)
cfi_flash.c:1857:6: warning: symbol '__flash_cmd_reset' was not declared. Should it be static?
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives. Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h. They come with 'const' added for some swab functions, so
fix those up, too:
include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]
Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).
We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:
macb.c:54:0: warning: "barrier" redefined [enabled by default]
In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)). This fixes
arch/powerpc/lib/bootm.c:
bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token
powerpc sparse builds yield:
include/common.h:356:22: error: marked inline, but without a definition
the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'
also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]
and:
Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here
and:
In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
Add the missing bits to the Tegra NAND driver to make ONFI detection work
properly.
Also add it to the Tegra default config, as it seems to be a reasonable thing
to have it available on all boards that use any kind of NAND.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Boards may require a different pinmux setup for NAND than the default one.
Add a way to call into board specific code to set this up.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.
All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Due to grown code sizes the TQM85xx boards don't build any more with
some older tool chains (like ELDK 4.2). As these boards have long
reached EOL it seems a waste of effort trying to fix them. The vendor
has agreed to drop support for them, too. So let's get rid of them.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
Use the same IP revisions as in Linux in order to make the comparison more
clear.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Merge mxc_setup_config1() into board_nand_init() in order to ease the addition
of i.MX5 support in the following patches.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
mxc_nand_read_page_raw_syndrome() should reenable ECC upon exit. This fixes ECC
errors left uncorrected after a call to this function.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use _mxc_nand_enable_hwecc() instead of duplicating its code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
On the NFC IP 1.1, the 32-bit ecc_status_result value comes from 2
consecutive 16-bit registers. This patch reads all the fields of this value,
which makes a difference for 4-kiB NF pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patches fixes the TODO to use same register definitions in mtd mxc_nand and
nand_spl fsl nfc drivers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This is based on Linux kernel -next:
commit 14f44abf1dafc20ba42ce8616a8fc8fbd1b3712b
Author: Brian Norris <computersforpeace@gmail.com>
Date: Fri Jul 13 09:28:24 2012 -0700
mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is not
the same as others. Instead of bit 1 being lock, it is #lock_tight.
To make the driver support either format, ignore bit 1 and use only
bit 0 and bit 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
