Commit graph

22815 commits

Author SHA1 Message Date
Fabio Estevam
fc740648bd mx6: soc: Staticize set_vddsoc()
set_vddsoc() is not used anywhere else, so make it static.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Fabio Estevam
5dc64ab730 mx6sabre_common.h: Add CONFIG_CMD_FUSE support
Add CONFIG_CMD_FUSE option, so that the fuse API can be used.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2014-01-02 17:16:50 +01:00
Fabio Estevam
6f3bef9e30 doc: README.fuse: Add an example on how to use the fuse API on mx6q
When using the fuse API in U-boot user must calculate the 'bank' and 'word'
values.

Provide a real example on how to calculate such values for the mx6q.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2014-01-02 17:16:50 +01:00
Marek Vasut
9b56942f7d mtd: onenand: Fix unaligned access
Fix unaligned access in OneNAND core. The problem is that the ffchars[] array
is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed
to the memcpy_16() function. The memcpy_16() function will treat the buffer as
an array of "unsigned short", thus triggering unaligned access if the compiler
decided ffchars[] to be not aligned.

I managed to trigger the problem with regular ELDK 5.4 GCC compiler.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2013-12-31 09:59:16 +01:00
Piotr Wilczek
a5e15bbb42 board:trats2: fix default partitions and mmc env
This patch add uuid disk to defualt partions necessary to
restore gpt partitions and fixes mmcdev environmental variable.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-31 16:41:10 +09:00
Piotr Wilczek
ef23b99607 board:trats1:trats2: fix adapter number
This fix is necessary after increased by one the number
of adapters in s3c24x0 driver.

Tested on Trats and Trats2.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-31 16:41:10 +09:00
Rajeshwari Birje
0fcac1abde SPL: EXYNOS: Prepare for variable size SPL support
When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.

The enhancements include
	- adding a command line option, '--vs' to indicate the need for the
	variable size encapsulation
	- padding the fixed size encapsulated blob with 0xff instead of random
	memory contents
	- do not silently truncate the input file, report error instead
	- no need to explicitly closing files/freeing memory, this all happens
	on exit; removing cleanups it makes code clearer
	- profuse commenting
	- modify Makefile to allow enabling the new feature per board

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:35 +09:00
Rajeshwari Birje
76dd9b6a63 Config: Add initial config for SMDK5420
Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:35 +09:00
Rajeshwari Birje
e2be3369c8 DTS: Add dts support for SMDK5420
This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:35 +09:00
Rajeshwari Birje
e106bd9b9d Exynos5420: Add base patch for SMDK5420
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
5af4a4f74a Exynos5420: Add support for 5420 in pinmux and gpio
Adds code in pinmux and gpio framework to support Exynos5420.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
f3d7c2fe9d Exynos5420: Add DDR3 initialization for 5420
This patch intends to add DDR3 initialization code for Exynos5420.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
060c227a28 Exynos5420: Add clock initialization for 5420
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
e89278c933 EXYNOS5420: Add dmc and phy_control register structure
Add dmc and phy_control register structure for 5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
3e97635764 EXYNOS5420: Add power register structure.
Add structure for power register for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
e69847ab8d Exynos5420: Add base addresses for 5420
Adds base addresses of various IPs and controllers required for
Exynos5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
71ebb33559 EXYNOS5: Create a common board file
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.

exynos_init function is provided for platform specific code.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Tom Rini
2d51bc3036 PowerPC: Drop linkstation_HGLAN support
With changes to the rtl8169 ethernet to improve cache support, we have
needed additional cache functions for mpc8245.  As the board maintainer
has been unresponsive, remove this board.

Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-20 11:24:07 -05:00
Łukasz Majewski
fef24f4f38 ARM: Samsung: Change GONI and Universal_C210 maintainers.
Update boards.cfg entries for Samsung's GONI and Universal_C210 maintainers
entry.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-20 10:48:06 -05:00
Tom Rini
1bbba03d0e Merge branch 'master' of git://git.denx.de/u-boot-spi 2013-12-19 14:22:12 -05:00
Stefano Babic
f5514e47c4 MX6: fix sata compilation for i.MX6
Commit 164d984661 breaks
board with SATA support, because sata is not compiled.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-12-19 11:04:33 +01:00
Poddar, Sourav
ac5cce38de driver: mtd: sf_ops: claim bus while doing memcpy
claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-19 12:23:22 +05:30
Poddar, Sourav
2c57b03bab config: dra7_evm: Add Bank Address Register(BAR) config
Add config to support bank address register.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-19 12:23:21 +05:30
Lokesh Vutla
2931fa4db3 ARM: AM43xx: Add Maintainer
Adding Maintainer for AM43xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:45 -05:00
Lokesh Vutla
b5e01eecc8 ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:45 -05:00
Lokesh Vutla
d3daba10f1 ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:44 -05:00
Lokesh Vutla
965de8b91b ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-18 21:14:18 -05:00
Lokesh Vutla
cf04d0326b ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50	300MHz
OPP100	600MHz
OPP120	720MHz
OPPTB	800MHz
OPPNT	1000MHz
According to the latest DM following is the OPP table dependencies:
	VDD_CORE 	VDD_MPU
	OPP50		OPP50
	OPP50 		OPP100
	OPP100		OPP50
	OPP100		OPP100
	OPP100		OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
4892495e36 ARM: AM43xx: mux: Update mux data
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
1fb68b842e ARM: AM43xx: Update Current Booting devices list
Current Booting devices list is different from that of AM33xx.
Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
0d54cb924e ARM: AM43xx: Select clk source for Timer2
Selecting the Master osc clk as Timer2 clock source.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Sekhar Nori
f4af163e6c ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Sekhar Nori
9f1a8cd33f ARM: AM43XX: board: add support for reading onboard EEPROM
Add support for reading onboard EEPROM to enable
board detection.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
1564dba7d9 ARM: AM43xx: Add extra ENV settings
Add Extra env settings.
This is derived from am335x Extra ENV settings.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
573b020ecb ARM: AM43xx: Add L2 Support
AM4372 uses PL310 L2 Cache. Enable the configs for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
369cbe1e1e ARM: AM43xx: Adapt to ti_armv7_common.h config file
Use ti_armv7_common.h config file to inclde the common
configs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
7ca1b2a210 ARM: AM43xx: Update the base addresses of modules
PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:13:59 -05:00
Stefan Roese
ce23b18bbb arm: omap3: Fix beagleboard SPL boot hangup (GPIO clocks not enabled)
Patch f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Beagleboard. Since some gpio input's are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
2013-12-18 21:13:59 -05:00
Tom Rini
ef184040b7 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2013-12-18 18:45:39 -05:00
Albert ARIBAUD
d627eefcd5 Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2013-12-18 22:19:02 +01:00
Albert ARIBAUD
fe7f0810dd Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2013-12-18 21:45:34 +01:00
Tom Rini
2d65256bb0 Merge branch 'master' of git://git.denx.de/u-boot-usb 2013-12-18 15:06:43 -05:00
Marek Vasut
f90aea2a65 ARM: pxa: Fix CONFIG_SYS_HZ on PXA
The PXA incorrectly uses CONFIG_SYS_HZ, which should be 1000 across
U-Boot. Fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2013-12-18 20:40:05 +01:00
Marek Vasut
eb63218b9b usb: ehci: Fix register access
Fix the register access in EHCI HCD. We need to use address of the register
as an ehci_writel() argument.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2013-12-18 19:53:19 +01:00
Marek Vasut
1e1be6d478 usb: ehci: Do not de-init uninited controllers
In case the controller is not initialized, we shall not de-initialize it.
As the control structure will not be filled, we will produce a null ptr
dereference if the controller is not inited.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2013-12-18 19:53:19 +01:00
Marek Vasut
8fb83547b9 usb: ehci-pci: Clarify and cleanup the EHCI controller detection
The detection function of the EHCI PCI controller was really cryptic,
add a beefy comment and clean the portion of the code up a bit. No
change in the logic of the code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2013-12-18 19:53:19 +01:00
Lukasz Majewski
3990994c43 ARM: trats: dfu: Enable default Poll Timeout for Trats board
Provide default Poll Timeout value for Trats board.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2013-12-18 19:53:19 +01:00
Lukasz Majewski
77b9504288 usb: f_dfu: cosmetic: Code cleanup
Code cleanup for dfu_bind_config function

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2013-12-18 19:53:19 +01:00
Lukasz Majewski
33fac4a6a2 usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout value
It is necessary to deter the host from sending subsequent DFU_GETSTATUS
request in the case of e.g. writing the buffer to medium.

Here the timeout is increased when we fill up the whole buffer. This delay
allows eMMC memory to perform its internal operations.
Otherwise we end up with HOST's error regarding GET_STATUS receive timeout.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2013-12-18 19:53:19 +01:00
Lukasz Majewski
4fb127898e dfu: Export allocated dfu buffer size
The method for exporting size of allocated buffer is provided.
It is afterwards used by USB's dfu function code.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2013-12-18 19:53:19 +01:00