Commit graph

24414 commits

Author SHA1 Message Date
Nobuhiro Iwamatsu
dbfd1159ab arm: rmobile: koelsch: Fix QoS revision 0.240 and 0.320
Add register define of DBSC3 operation adjustment register,
and add initial value.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
dd73018b16 arm: rmobile: r8a7791: Fix MOD_SEL3 function table about FN_SEL_IEB
FN_SEL_IEB is assigned 2bit, and 2bit can represent 4 patterns.
However FN_SEL_IEB but we only use 3. It adds empty patterns as 0.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
b6c96f7f35 arm: rmobile: koelsch: Add support ext4/fat write command
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
d80149b249 arm: rmobile: lager: Add support ext4/fat write command
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
f55bb6a4c4 arm: rmobile: lager: Add support command and filesystems of VFAT
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
5c4bb96e9c arm: rmobile: lager: Add support USB controller
Lager board has USB ports. This add support of USB controller of rmobile.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
fd77b2ebec arm: rmobile: koelsch: Add support command and filesystems of VFAT
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
aa44ae32e1 arm: rmobile: koelsch: Add support USB controller
Koelsch board has USB ports. This add support of USB controller of rmobile.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
7880356b89 gpio: r8a7790-gpio: Fix typo in macro
Fix typo from __ASM_R8A7790_H__ to __ASM_R8A7790_GPIO_H__.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
f2c51fdc93 gpio: r8a7791-gpio: Fix typo in macro
Fix typo from __ASM_R8A7791_H__ to __ASM_R8A7791_GPIO_H__.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
7f922e32ff arm: rmobile: lager: Enable optimization of thumb
This adds CONFIG_SYS_THUMB_BUILD to config, in order to enable optimization
of thumb.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
05aad15bba arm: rmobile: lager: Remove CONFIG_USE_ARCH_MEMSET and MEMCPY
Because do not need these feature to lager board, this delete it.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
b923d4615f arm: rmobile: lager: Remove define of SCIF register
The define of SCIF register was already defined in rcar-base.h.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
e1ee37472b arm: rmobile: koelsch: Enable optimization of thumb
This adds CONFIG_SYS_THUMB_BUILD to config, in order to enable optimization
of thumb.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
a6318a8c61 arm: rmobile: koelsch: Remove CONFIG_USE_ARCH_MEMSET and MEMCPY
Because do not need these feature to koelsch board, this delete it.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
577d07ac9d arm: rmobile: koelsch: Remove define of SCIF register
The define of SCIF register was already defined in rcar-base.h.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:18 +09:00
Nobuhiro Iwamatsu
e6f2c20689 arm: rmobile: Add define of SCIF register for R8A7790 and R8A7791
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:18 +09:00
Siva Durga Prasad Paladugu
1a897668ac fpga: Added support to load bit stream from SD/MMC
Added support to load a bitstream image in chunks by reading it in
chunks from SD/MMC.
Command format:
loadfs [dev] [address] [image size] [blocksize] <interface>
       [<dev[:part]>] <filename>
Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
26ea9ce5b8 zynq: Enable fpga loadp and loadbp commands
Use new fpga commands for loading partial bitstreams.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
5b815c9c61 fpga: zynqpl: Clean partial bitstream handling
Do not do partial bitstream detection based on bitstream
size and use bitstream_type argument which is passed
from the fpga core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
67193864bc fpga: Add support to load partial bitstreams
Added support to load partial bitstreams.
The partial bitstreams can be loaded using the below commands
Commands:
fpga loadp <dev> <addr> <size>
fpga loadbp <dev> <addr> <size>
The full bit streams can be loaded using the
old commands(fpga load and fpga loadb).

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
7a78bd2679 fpga: Define bitstream type based on command selection
Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Siva Durga Prasad Paladugu
64e809afea fpga: Guard the LOADMK functionality with CMD_FPGA_LOADMK
Guard the LOADMK functionality with config to provide
an option to enable or disable it.
Enable it for all platforms in mainline which enable CONFIG_CMD_FPGA.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
d0db28f940 configs: iocom: Fix typo on CMD_FPGA command
Fix typo in CMD_FPGA command enabling.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Albert ARIBAUD
05d134b084 Merge remote-tracking branch 'u-boot/master'
Conflicts:
	boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
2014-05-20 10:05:42 +02:00
Albert ARIBAUD
6130c14605 boards.cfg: reformat
Apply command "tools/reformat.py -i -d '-' -s 8 <boards.cfg
>boards0.cfg && mv boards0.cfg boards.cfg" in preparation of
pull request from ARM to main tree.
2014-05-20 09:31:40 +02:00
Tom Rini
d7782d0653 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-05-16 18:30:33 -04:00
Liu Gang
e4911815cf powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE boot
The new 768KB u-boot image size requires changes for
SRIO/PCIE boot. These addresses need to be updated to
appropriate locations.

The updated addresses are used to configure the SRIO/PCIE
inbound windows for the boot, and they must be aligned
with the window size based on the SRIO/PCIE modules requirement.
So for the 768KB u-boot image, the inbound window cannot be set
with 0xfff40000 base address and 0xc0000 size, it should be
extended to 1MB size and the base address can be aligned with
the size.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:29:16 -05:00
Kim Phillips
3246584d19 mpc85xx: configs: remove c=ffe from default environment
AFAICT, c=ffe does nothing and was a typo from the original commit
d17123696c "powerpc/p4080: Add support
for the P4080DS board" and just kept on getting duplicated
in subsequently added board config files.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Edward Swarthout <ed.swarthout@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:27:05 -05:00
Prabhakar Kushwaha
bc2d40ca10 board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL
In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
Aneesh Bansal
3051f3f999 powerpc/mpc85xx: SECURE BOOT- corrected CSPR settings for BSC9132QDS NAND
In case of secure boot from NAND, CSPR and FTIM settings are
same as non-secure NAND boot. CSPR0 is configured as NAND and
CSPR1 is configured as NOR.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
ramneek mehresh
80ba6a6f2a mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platform
P1020 SoC which has two USB controllers, but only first one is used
on this platform.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
Nikhil Badola
15231f6dd1 drivers/usb : Define usb control register mask for w1c bits
Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
Shaveta Leekha
9c3fdd883a powerpc/mpc85xx: Added B4460 support
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Chunhe Lan
1a344456a9 powerpc/85xx: Add T4160RDB board support
T4160RDB shares the same platform as T4240RDB. T4160 is
a low power version of T4240, with the eight e6500 cores,
two DDR3 controllers, and same peripheral bus interfaces.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Chunhe Lan
f1a96ec1a9 fsl/pci: Add workaround for erratum A-005434
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Tang Yuantian
0f1fa36fff powerpc/t104xrdb: Toggle deep sleep management signals after resume
T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Ebony Zhu
477c894ff4 board/freescale: Move CRC32 offset in NXID v1 data format
According to AN3638, CRC of NXID v1 is at the end of the
256-byte I2C memory. The wrong CRC32 offset prevents Uboot
from reading system information from EEPROM. No NXID v0 is
being used on Freescale boards.

Signed-off-by: Ebony Zhu <b45385@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:05 -05:00
Chunhe Lan
ffc8667acf net: phy/vitesse: Add support for VSC8664 phy module
This patch adds support for VSC8664 PHY module which can
be found on Freescale's T4240RDB boards.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:05 -05:00
Albert ARIBAUD
a26acb7dc9 Merge remote-tracking branch 'u-boot-sh/rmobile'
Conflicts:
	boards.cfg

Trivial conflict, maintainer change plus board addition
2014-05-16 20:43:04 +02:00
Simon Glass
6be6b6bcba patman: Suppress duplicate signoffs only for real patches
There is an unfortunate bug in the signoff suppression logic. The first
pass is performed with 'git log', and all signoffs are added to the
supression set, such that the second time (when processing the real
patches) we always suppress the signoffs.

Correct this by only suppressing signoffs in the second pass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Michal Simek <monstr@monstr.eu>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-05-16 11:42:29 -07:00
Masahiro Yamada
2dabac1337 sandbox: set sandbox's vendor to null
Because sandbox is not a real hardware, setting vendor=sandbox is
almost meaningless.

This commit sets sandbox's vendor field to '-'.

It is a good thing that it decreases one level directory hierarchy.
The files board/sandbox/sandbox/* have been moved to board/sandbox/*.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-05-16 11:41:22 -07:00
Masahiro Yamada
c6eb9458e8 Revert "sandbox: move source files from board/ to arch/sandbox/"
This reverts commit 258060905e.

Conflicts:
	boards.cfg

Wrong patch 25806090 was applied by accident. Revert it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-05-16 11:40:51 -07:00
Albert ARIBAUD
6a2f30a03a Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-05-16 17:56:50 +02:00
Albert ARIBAUD
a90bed77a6 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-05-16 16:49:50 +02:00
Jaehoon Chung
73e3bea966 ARM: exynos5420: removed undefined gpio structure
It's removed the exynos5_gpio_part1.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:59:45 +09:00
Jaehoon Chung
9b8c9a3c09 mmc: s5p_sdhci: add the s5p_sdhci_core_init function
To reuse the code, added the s5p_sdhci_core_init function.
Before applied this patch, didn't use the 8-bit mode at exynos baord.
Because it didn't set "MMC_MODE_8BIT".

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
e33daad0b7 ARM: exynos4: enable the dwmmc configuration
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
e09bd85329 mmc: exynos_dw_mmc: enable the DDR mode
Set the ddr mode capability by default.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
ea5ee2d7fb ARM: dts: exnyos: enable dw-mmc controller
Enabled the dw-mmc controller.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00