* add parameters for factory and print them at start up to
facilitate control of right DDR3 settings in EEPROM.
* cosmetic changes in a couple of printfs
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
For dxr2 board DXR2_IOCTRL_VAL is set by data in EEPROM. In pxm2
board it does not make sense to have dxr2 as prefix. Replace it with
more meaningful DDR prefix.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Pascal Bach <pascal.bach@siemens.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.
Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:
repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]
According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.
At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.
An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.
While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Bard Liao <bardliao@realtek.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Venice2 pinmux spreadsheet was updated to fix a few issues. Import
those changes into the U-Boot pinmux initialization tables.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This re-imports the entire Venice2 pinmux data from the board's master
spreadsheet, and makes use of the new IO clamping GPIO initialization
table features. This makes the board port fully compliant with the
required HW-defined pinmux initialization sequence.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Modify the Jetson TK1 board to do this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. This patch implements this
procedure for Jetson TK1. For pins which are to be used as GPIOs, the
pinmux mux function need not be programmed, so the pinmux table is also
adjusted.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a function to the pinmux driver to allow boards to do this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. Add a feature to the GPIO driver
which executes a GPIO configuration table. Board files will use this to
implement the correct HW initialization procedure.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change
the mux option in HW.
For pins that will be used as GPIOs, the mux option is irrelevant, so we
simply don't want to define any mux option in the pinmux initialization
table.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c
enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment
implies. Fix the comment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
If CONFIG_API is ever to be enabled on Tegra, this define must be set,
since api/api_storage.c uses it.
A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE
1) It isn't documented in README. The same is true for a lot of similar
defines used by api_storage.c.
2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the
valid values are 0..n-1 not 0..n.
However, I this patch does not address those shortcomings.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
"make ep8248_config" fails with an error like this:
$ make ep8248_config
make: *** [ep8248_config] Error 1
Its cause is that there are two entries for "ep8248".
The first is around line 652 of boards.cfg. (as Active)
The second appears around line 1230. (as Orphan)
This bug was accidentally introduced by commit e7e90901.
But it is not the author's fault. He just intended to change
IDS8247 board.
The commiter added ep8248 entry by mistake when he resolved a conflict.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Kim Phillips <kim.phillips@linaro.org>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
This patch converts the following boards to use generic board: MPC8536DS,
MPC8572DS, MPC8641HPCN, p1_p2_rdb_pc, corenet_ds, t4qds, B4860QDS. It has
been tested on NOR boot on MPC8536DS, MPC8572DS, P1021RDB, P4080DS,
P5020DS, P5040DS, P3041DS, T4240QDS, B4860QDS.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Ying Zhang <b40530@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Haijun.Zhang <Haijun.Zhang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Shaohui Xie <Shaohui.Xie@freescale.com>
The argument boot_flag of board_inti_f() hasn't been used for powerpc until
recent changing to use generic board. Set it to 0 as a proper value.
Signed-off-by: York Sun <yorksun@freescale.com>
baord_init_f takes one argument, boot_flag. It has not been used for
powerpc, until recently changing to use generic board architecture.
The boot flag is added as a return value from cpu_init_f().
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
The return value has not been checked by its caller, until recent change
of using generic board architecture. The error of this function is not
critical enough to hang the system. Printing the warning message is enough
to catch user's attention. U-boot should continue to boot to give user
a chance to fix the EEPROM. Chaning the return value to 0 to avoid hanging
in the board_init_r().
Signed-off-by: York Sun <yorksun@freescale.com>
The pointer of device tree comes from r3 for QEMU. This is not the case
for normal SoCs out of reset. Having gd->fdt_blob as 0 is important for
other functions to detect the non-existence of device tree.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
U-boot image has grown and exceeded the predefined 512KB. Increasing to
768KB to align with other powerpc boards. Tested on MPC8572DS for 32-
and 36-bit targets with NOR flash boot. NAND boot is not covered by
this patch.
Also update board maintainer for these boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
when qe-ucode fails to be uploaded, "deep sleep" will hang.
if there is no qe-ucode, disable qe module for platforms
which support "deep sleep"
Signed-off-by: Zhao Qiang <B45475@freescale.com>
We want to use the TLB mapping helpers in relocated mode as well. These helpers
need to have awareness of already occupied TLB entries. We already had them in
sync in non-relocated mode, but need to resync them when we move into relocated.
Signed-off-by: Alexander Graf <agraf@suse.de>
For the QEMU machine type, we can plug in either e500v2, e500mc, e5500
or e6500 style cores into the system. U-boot has to work with all of them.
So avoid using HID1 which is not available on e500mc systems to make sure
we don't trap on it.
Signed-off-by: Alexander Graf <agraf@suse.de>
We only need u-boot to bother about a single core in the QEMU machine.
Everything that would require additional knowledge of more cores gets
handled by QEMU and passed straight into the payload we execute.
Because of this setup, it would be counterproductive to enable SMP support
in u-boot. We would have to rip CPUs out of already existing spin tables
and respin them from u-boot. It would be a pretty big mess.
So only assume we have a single core. This fixes errors about CONFIG_MP
being disabled.
Signed-off-by: Alexander Graf <agraf@suse.de>
This should prevent the problems that the CCF can deadlock with certain
traffic patterns.
This also fixes the workaround for A-006559 that was not correctly
implemented before.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Fix the IRQ/GPIO settings: all the muxed GPIO/external IRQs that are
used as internal interrupts are defined as GPIOs to avoid confusion
between the internal/external interrupts.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This adds the reset support for the following devices that was until
then not implemented:
- BFTIC4
- QSFPs
This also fixes the configuration of the prst behaviour for the other
resets: Only the u-boot and kernel relevant subsystems are taken out of
reset (pcie, ZL30158, and front eth phy).
Most of the prst config move to misc_init_f(), except for the PCIe
related ones that are in pci_init_board and the bftic and ZL30158 ones
that should be done as soon as possible.
Only the behavior of the Hooper reset is changed according to the
documentation as the application is not able to not configure the switch
when it is not reset.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This prevents u-boot from accessing into the reserved memory areas that
we have for /var and the logbooks.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This patch defines the post_hotkeys_pressed() function that is used for:
- triggering POST memory regions test
- starting the test application through the checktestboot command in
a script by setting the active bank to testbank
The post_hotkeys_pressed return the state of the SELFTEST pin.
The patch moves from the complete POST-memory test that is too long in
its SLOW version for our production HW test procedure to the much shorter
POST-memory-regions test.
Finally, the unused #defines for the not so relevant mtest command are
removed.
Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Add readout of dip-switch to revert to factory settings.
If one or more dip-switch are set, launch bank 0 that contains the
bootloader to do the required action.
Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
The unit LEDs are managed by the QRIO CPLD. This patch adds support for
accessing these LEDs in the QRIO.
The LEDs then are set to a correct boot state:
- UNIT-LED is red
- BOOT-LED is on.
Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO
access, this is due to an errata A-006260 on T4 rev1.0 which is fixed
on rev2.0, so remove the maximum value to use the default value for rev2.0.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Secure Boot Target is added for T2080RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
T1040RDB.h file is removed and a unified file T104xRDB.h is created.
Hence macro CONFIG_T1040 is renamed to CONFIG_T104x.
Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
T4240RDB board Specification
----------------------------
Memory subsystem:
6GB DDR3
128MB NOR flash
2GB NAND flash
Ethernet:
Eight 1G SGMII ports
Four 10Gbps SFP+ ports
PCIe:
Two PCIe slots
USB:
Two USB2.0 Type A ports
SDHC:
One SD-card port
SATA:
One SATA port
UART:
Dual RJ45 ports
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.
B4860QDS has a PowerOne ZM7300 programmable digital Power
Manager which is programmed as per the value read from
the fuses.
Reference for this code is taken from t4qds VID implementation.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Adds Support for PowerOne ZM7300 voltage regulator.
This device is available on some Freescale Boards like B4860QDS
and has to be programmed to adjust the voltage on the board.
The device is accessible via I2C interface.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Use helper function zynq_validate_bitstream so that the
code can be reused easily for different cases of dma transfer.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use zynq_dma_xfer_init, zynq_align_dma_buffer,
zynq_dma_transfer helper function performing dma
transfers so that the code can be reused easily for
different cases of dma transfer.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Warnings:
drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer
drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
