Commit graph

129 commits

Author SHA1 Message Date
Shaveta Leekha
652e29b4a0 board/b4qds: VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.

B4860QDS has a PowerOne ZM7300 programmable digital Power
Manager which is programmed as per the value read from
the fuses.

Reference for this code is taken from t4qds VID implementation.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2014-05-13 08:20:31 -07:00
Prabhakar Kushwaha
9307cbaba9 powerpc/mpc85xx:Update MONITOR_LEN for 768KB u-boot size
U-boot binary size has been increased from 512KB to 768KB.

So update CONFIG_SYS_MONITOR_LEN to reflect the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
c5dfe6ec58 board/b4qds:Add support of 2 stage NAND boot-loader
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
  - Add spl.c which defines board_init_f, board_init_r
  - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Zhao Qiang
dcf1d774bf QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Masahiro Yamada
e4536f8e37 freescale: pblimage: refactor CONFIG_SYS_FSL_PBL_{PBI, RCW}
Pull out "$(SRCTREE)/" from CONFIG_SYS_FSL_PBL_PBI
and CONFIG_SYS_FSL_PBL_RCW and push it into the top Makefile.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2014-03-12 17:04:49 -04:00
Masahiro Yamada
d40ddae4b3 powerpc: mpc85xx: move CONFIG_MPC85xx definition to CPU config.mk
Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk
because all target boards with mpc85xx cpu define it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Prabhakar Kushwaha
e222b1f36f powerpc/mpc85xx:Increase binary size for P, B & T series boards.
u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.

So, Increase the u-boot binary size to 768KB.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-01-21 14:06:30 -08:00
Prabhakar Kushwaha
690e425844 powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI
Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.

Also add their details in README.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 14:02:41 -08:00
York Sun
ab13ad5835 powerpc/B4860QDS: Define new nand_ecclayout structure macros
Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
reduce the image size, by taking advantage of the new nand_ecclayout
structure.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
2014-01-02 14:10:13 -08:00
Vladimir Zapolskiy
2c808a12ea kgdb: configs: remove obsolete CONFIG_KGDB_SER_INDEX
The last users of CONFIG_KGDB_SER_INDEX were removed more than 3 years
ago in commits 550650ddd0 and bf16500f79, either kgdb subsystem should
care about this parameter or it should be gone completely.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2013-12-13 09:15:32 -05:00
York Sun
5614e71b49 Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:43 -08:00
Rob Herring
cdb23792e8 config: remove platform CONFIG_SYS_HZ definition part 1/2
Remove platform CONFIG_SYS_HZ definition for configs A-Z*.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:05:59 -05:00
Rob Herring
0defddc851 config: Add a default CONFIG_SYS_PROMPT
The definitions for CONFIG_SYS_PROMPT are varied with little reason other
than to display the board name. Over half the definitions are "==> ", so
make this the default. The rest of the boards remain unchanged to avoid
breaking any external scripts expecting a certain prompt.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-11-04 11:02:14 -05:00
Shaohui Xie
83d925668f powerpc/B4860: enable PBL tool for B4860
Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16 16:13:12 -07:00
Po Liu
0d2cff2d9e powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h
This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-10-16 16:13:10 -07:00
Minghuan Lian
0795eff34c powerpc/rman: fix RMan support for t4240 and b4860
1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860.
2. Decrease RMan liodn offset number.
SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3.
For t4240 and b4860, RMan liodn base is assigned to 922, the original
offset number is too large that the liodn (base+offset 922+678 = 1600)
is greater than 0x500 the maximum liodn number.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:41 -07:00
Shaveta Leekha
cb033741f4 board/b4860qds: Add support for configuring SerDes1 Refclks
1) Add support in B4860 board files for using IDT driver where
   IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
   that generate different refclks for SerDes modules, used this driver
   for reconfiguring SerDes1 Refclks(based on SerDes1 protocols)
   for CPRI to work. CPRI works on 122.88MHz and default refclks coming
   on board are not suitable for it
2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file
   to b4860qds board file, as SerDes1 Refclk1 would come from
   PHY MUX in case of certain protocols, that have been checked here.
   This change would make on board SGMIIs to work
3) Add I2C addresses for IDT8T49N222A devices in board/include file
4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:41 -07:00
York Sun
d2ab4bbc7b powerpc/corenet: Move CONFIG_FSL_CORENET out of board header file
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
Tom Rini
c2120fbfbc Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.

Conflicts:
	board/sandburst/common/ppc440gx_i2c.c
	board/sandburst/common/ppc440gx_i2c.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:24 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Heiko Schocher
00f792e0df i2c, fsl_i2c: switch to new multibus/multiadapter support
- added to fsl_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
2013-07-23 08:34:53 +02:00
Prabhakar Kushwaha
4d0e6e0d73 board/b4860qds: Relax NOR flash teadc timing parameter
Relax parameters to give address latching more time to setup.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Liu Gang
5870fe44b2 powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Liu Gang
3a01799b35 powerpc/b4860qds: Enable master module for boot from SRIO and PCIE
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.

You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Gabor Juhos
842033e696 pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option
The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.

Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if this options is enabled.

Also add the new option into the configuration
files of the boards which needs that.

Compile tested for powerpc, x86, arm and nds32.
MAKEALL results:

powerpc:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 641
  Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
  ----------------------------------------------------------
  Note: the warnings for ELPPC and MPC8323ERDB are present even
  without the actual patch.

x86:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 1
  ----------------------------------------------------------

arm:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 311
  ----------------------------------------------------------

nds32:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 3
  ----------------------------------------------------------

Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-06-07 14:17:01 -04:00
Shaveta Leekha
6eaeba23dd powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Poonam Aggrwal
8fa0102bcf powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h
B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Suresh Gupta
16d88f415a Enable XAUI interface for B4860QDS
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
	The PHY addresses of Teranetics PHY on XAUI riser card are assigned
	based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
	AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
York Sun
b5b06fb7b0 powerpc/b4860qds: Added Support for B4860QDS
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.

B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
  ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,  ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
  16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
  8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
  RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
  connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
  connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
  configuration reset source. The RCW source is set by appropriate
  DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
	- On-board eCWTAP controller with ETH and USB I/F
	- JTAG/COP 16-pin header for any external TAP controller
	- External JTAG source over AMC to support B2B configuration
	- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
	- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
  DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
  - total four refclk, including CPRI clock scheme

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:11 -06:00