The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry. Actually use the bit masks for these items
since they are only a single bit.
Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- support larger DDR memories up to 2G on the PC8540/8560ADS and
STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
- Add support for RPC/STx GP3, Motorola 8560 board
- Update 85xx TSEC driver so it searches MII for first available PHY
and uses that one.
- Add functions to support console MII commands.
* Patch by Tolunay Orkun, 07 Apr 2004:
Move initialization of bi_iic_fast[]
from board_init_f() to board_init_r()
* Patch by Yasushi Shoji, 07 Apr 2004:
Cleanup microblaze port
* Patch by Sangmoon Kim, 07 Apr 2004:
Add auto SDRAM module detection for Debris board
