Commit graph

300 commits

Author SHA1 Message Date
Stephen Warren
1163625898 Rename reset to sysreset
The current reset API implements a method to reset the entire system.
In the near future, I'd like to introduce code that implements the device
tree reset bindings; i.e. the equivalent of the Linux kernel's reset API.
This controls resets to individual HW blocks or external chips with reset
signals. It doesn't make sense to merge the two APIs into one since they
have different semantic purposes. Resolve the naming conflict by renaming
the existing reset API to sysreset instead, so the new reset API can be
called just reset.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-05-26 20:48:31 -06:00
Andreas Bießmann
09c2b8f3e3 Change my mailaddress
I'll switch my mails to my own server, so drop all gmail references.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-05-02 18:37:09 -04:00
Andreas Dannenberg
f00169a915 arm: spl: Align default board_init_f comment with code
The default board_init_f() implementation performs a call to
board_init_r() as the last step of the sequence. Fix the comment
for this function to reflect the actual execution flow.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2016-04-01 17:17:57 -04:00
Alexander Graf
d990f5c834 arm: Add support for HYP mode and LPAE page tables
We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.

So this patch introduces support for both long descriptor PTEs and HYP mode
registers.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-27 09:12:17 -04:00
Prabhakar Kushwaha
2b690b9837 armv8: lsch3: Enable WUO config for RNI-20 node
Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.

WRIOP IP is connected to RNI-20 Node.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Simon Glass
9ab60493c9 arm: Add a 64-bit division routine to the private library
This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.

Code is available for using the CLZ instruction but it is not enabled at
present.

This comes from coreboot version 4.0.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:27 +08:00
Alexander Graf
cc4a474873 arm: Allow EFI payload code to take exceptions
There are 2 ways an EFI payload could return into u-boot:

  - Callback function
  - Exception

While in EFI payload mode, r9 is owned by the payload and may not contain
a valid pointer to gd, so we need to fix it up. We do that properly for the
payload to callback path already.

This patch also adds gd pointer restoral for the exception path.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 21:30:13 -04:00
Alexander Graf
649829157e arm64: Allow EFI payload code to take exceptions
There are 2 ways an EFI payload could return into u-boot:

  - Callback function
  - Exception

While in EFI payload mode, x18 is owned by the payload and may not contain
a valid pointer to gd, so we need to fix it up. We do that properly for the
payload to callback path already.

This patch also adds gd pointer restoral for the exception path.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 21:30:11 -04:00
Alexander Graf
50149ea37a efi_loader: Add runtime services
After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.

This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.

We could maybe in the future map U-boot environment variables to EFI variables
here.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-03-15 18:03:10 -04:00
David Müller (ELSOFT AG)
03a3a8aec8 arm: make sure board_init_r() is being called using the right mode (ARM / THUMB)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-15 12:04:45 -05:00
Marek Vasut
a592e6fb7f arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7
The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured for the
cache on ARMv7 to operate correctly.

The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
issues which are hard to replicate, for example certain USB sticks are not
detected or QSPI NOR sometimes fails to write pages completely.

The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
correct because the code which added the test(s) for CONFIG_ARMV7 was added
shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
not adjusted correctly to reflect that change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
2016-01-31 16:32:56 +01:00
Jeffy Chen
f7ee071a22 ARM: bootm: Try to use relocated ramdisk
After boot_ramdisk_high(), ramdisk would be relocated to
initrd_start & initrd_end, so use them instead of rd_start & rd_end.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-21 20:03:59 -07:00
Stephen Warren
a737028e80 arm: initialize gd for AArch64
Commit adc421e4ce "arm: move gd handling outside of C code" removed
the call to arch_setup_gd() on ARM and replaced it with assembly code
in crt0.S. However, AArch64 uses a different startup file, and the same
change was not made to it. This leaves gd uninitialized on AArch64, which
typically leads to hangs or crashes. This change fixes that.

Fixes: adc421e4ce ("arm: move gd handling outside of C code")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2016-01-14 16:27:13 -05:00
Albert ARIBAUD
adc421e4ce arm: move gd handling outside of C code
As of gcc 5.2.1 for Thumb-1, it is not possible any
more to assign gd from C code, as gd is mapped to r9,
and r9 may now be saved in the prolog sequence, and
restored in the epilog sequence, of any C functions.

Therefore arch_setup_gd(), which is supposed to set
r9, may actually have no effect, causing U-Boot to
use a bad address to access GD.

Fix this by never calling arch_setup_gd() for ARM,
and instead setting r9 in arch/arm/lib/crt0.S, to
the value returned by board_init_f_alloc_reserve().

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-13 21:05:18 -05:00
Albert ARIBAUD
ecc306639e Fix board init code to respect the C runtime environment
board_init_f_mem() alters the C runtime environment's
stack it is actually already using. This is not a valid
behaviour within a C runtime environment.

Split board_init_f_mem into C functions which do not alter
their own stack and always behave properly with respect to
their C runtime environment.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
2016-01-13 21:05:17 -05:00
Kamil Lulko
5be9356926 Change e-mail address of Kamil Lulko
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
2015-12-05 18:22:32 -05:00
Peng Fan
bc3c89b130 common: bootm: check return value of strict_strtoul
Before continue, check return value of strict_strtoul.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-05 18:22:12 -05:00
Albert ARIBAUD
62e92077a8 arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.

This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-11-10 15:03:48 +01:00
Vadzim Dambrouski
7bdf75ca5c arm: fix compile warnings when semihosting is enabled on ARMv7M target.
This patch fixes compile warnings like this:

warning: format '%lu' expects argument of type 'long unsigned int',
         but argument 5 has type 'size_t'

In C99 standard you can use %zu modifier to print size_t values.

Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
2015-11-10 09:45:36 +01:00
Vadzim Dambrouski
432a6241bd arm: add support for semihosting for ARMv7M targets
If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile
error looking like this:

arch/arm/lib/semihosting.c: In function 'smh_read':
{standard input}: Assembler messages:
{standard input}:34: Error: invalid swi expression
{standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0
scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed

The source of the problem is "svc #0x123456" instruction. This instruction
can not be encoded using Thumb2 instruction set used by ARMv7M CPUs.
ARM documentation suggests using "bkpt #0xAB" instruction instead [1].
This patch fixes compile errors and adds support for semihosting for
STM32F429 or any other ARMv7M target.
This change was sested on STM32F429-DISCOVERY board using OpenOCD and
"smhload" u-boot command.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html

Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
2015-11-10 09:45:33 +01:00
Simon Glass
5ba534d247 arm: Switch 32-bit ARM to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24 13:50:36 -04:00
Simon Glass
931bec31b4 arm: Switch aarch64 to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Tested on LS2085ARDB and LS2085AQDS (armv8 SoC).
Tested-by: York Sun <yorksun@freescale.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24 13:50:36 -04:00
Thierry Reding
b1964c72bd armv8/gic: Fix GIC v2 initialization
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-15 14:47:03 +02:00
Albert ARIBAUD
13a3972585 Merge remote-tracking branch 'u-boot/master' 2015-10-14 10:46:36 +02:00
Simon Glass
1090a56c87 arm: Drop old non-generic-board code
This code is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@gmail.com>
2015-09-28 10:48:24 -04:00
Simon Glass
ed64190f67 arm: Correct comments in crt0.S for the recent SPL improvements
The current comments need a bit of tweaking since we now support stack
and global_data relocation in SPL. Also add a reference to the README.

For AArch64 this is not implemented, so leave a TODO for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tim Harvey <tharvey@gateworks.com>
2015-09-12 09:00:35 +02:00
Tom Rini
c9feb427ab Merge git://git.denx.de/u-boot-rockchip 2015-09-03 14:57:09 -04:00
Simon Glass
c6aabe9289 arm: reset: Avoid a build error when the reset uclass is enabled
There can be only one do_reset(). When CONFIG_RESET is enabled this is
provided by the reset uclass, and ARM's version should be disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:23 -06:00
Bhupesh Sharma
3ffa95c283 armv8: Add framework for CCN-504 interconnect configuration
This patch adds a minimal framework for Dickens CCN-504
interconnect configuration - mainly related to adding Clusters/cores
to snoop/DVM domain and setting QoS of the RN-I ports.

LS2085A platform makes use of these configurations to support
better network data performance and to boot a SMP Linux.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:37:49 -05:00
Tom Rini
b5d92ba1ad ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DM
We now have the CONFIG_SPL_DM for code within SPL to toggle caring about
DM or not.  Without this change platforms that do enable CONFIG_DM but
not CONFIG_SPL_DM may be broken (such as OMAP5).

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-12 20:48:07 -04:00
Wu, Josh
633b6ccedf ARM: cache: implement a default weak flush_cache() function
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.

In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.

So in this patch remove such code in flush_cache() and only call
flush_dcache_range().

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2015-08-12 20:47:48 -04:00
Wu, Josh
387871a10e ARM: cache: add an empty stub function for invalidate/flush dcache
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.

To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-12 20:47:47 -04:00
Heiko Schocher
80402f34f8 spl, common, serial: build SPL without serial support
This patch enables building SPL without
CONFIG_SPL_SERIAL_SUPPORT support.

Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Ensure we build arch/arm/imx-common on mx28]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-12 20:47:13 -04:00
Thierry Reding
502a2aff76 arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN values
The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN
can only accept certain values, and the set of acceptable values differs
between the AArch32 and AArch64 instructions sets. The default value of
CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default
value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0
assembly so it can handle completely arbitrary values.

Signed-off-by: Thierry Reding <treding@nvidia.com>
[twarren: trimmed Thierry's patch to remove changes already present]
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, cleaned up patch, wrote description, re-wrote subject]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-07-27 15:54:28 -07:00
Simon Glass
1251d51ca5 arm: Add ENTRY/ENDPROC to private libgcc functions
When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from
Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is
used to call these ARM functions, instead of plain BL, which will fail.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Pavel Machek <pavel@denx.de>
2015-07-07 11:39:22 +02:00
Matt Porter
f99993c108 common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.

Signed-off-by: Matt Porter <mporter@konsulko.com>
2015-05-28 08:18:23 -04:00
Tom Rini
4588d61a28 arch/arm/lib/bootm-fdt.c: Guard the include of <asm/armv7.h>
With d6b72da0 we started including this file unconditionally.  This
isn't allowed in a file that we also use on armv8.  This will get
cleaned up a bit better once we really start using these same features
(and have similar fdt updates needed) on armv8.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-05-14 11:07:03 -04:00
Jan Kiszka
d6b72da029 virt-dt: Allow reservation of secure region when in a RAM carveout
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.

Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons

This will be used in a subsequent patch for Jetson-TK1.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:14 -07:00
Jan Kiszka
104d6fb6cd ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:13 -07:00
Albert ARIBAUD
b939689c7b Merge branch 'u-boot/master' into 'u-boot-arm/master' 2015-05-05 10:09:06 +02:00
Tom Rini
3f6dcdb9cd Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-04-24 13:43:24 -04:00
Scott Wood
b2d5ac5985 armv8/ls2085aqds: NAND boot support
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
rev13@wp.pl
12d8a72913 ARM: Add ARMv7-M support
Signed-off-by: Kamil Lulko <rev13@wp.pl>
2015-04-22 12:14:55 -04:00
Joe Hershberger
d2eaec6006 net: Remove the bd* parameter from net stack functions
This value is not used by the network stack and is available in the
global data, so stop passing it around.  For the one legacy function
that still expects it (init op on old Ethernet drivers) pass in the
global pointer version directly to avoid changing that interface.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Trival fix to remove an unneeded variable declaration in 4xx_enet.c)
2015-04-18 11:11:11 -06:00
Joe Hershberger
0eb25b6196 common: Make sure arch-specific map_sysmem() is defined
In the case where the arch defines a custom map_sysmem(), make sure that
including just mapmem.h is sufficient to have these functions as they
are when the arch does not override it.

Also split the non-arch specific functions out of common.h

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Bryan Brinsko
97840b5d1f ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching
The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those issues.

Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
2015-04-16 14:59:33 +02:00
Tom Rini
692e5c4e7e Merge branch 'master' of git://git.denx.de/u-boot-tegra
Conflicts:
	board/armltd/vexpress64/vexpress64.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-04-03 09:14:38 -04:00
Linus Walleij
d5f3d17ca6 armv8: semihosting: delete external interface
Now that loading files using semihosting can be done using
a command in standard scripts, and we have rewritten the boardfile
and added it to the Vexpress64, let's delete the external
interface to the semihosting file retrieveal and rely solely
on these commands, and staticize them inside that file so the
whole business is self-contained.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:46 -04:00
Linus Walleij
202a674bb8 armv8: semihosting: add a command to load semihosted images
Instead of sprinkling custom code and calls over the Vexpress64
boardfile, create a command that loads images using semihosting
just like we would load from flash memory of over the network,
using a special command:

    smhload <image> <address>

This will make it possible to remove some custom calls and
code and make the boot easier.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:45 -04:00
Linus Walleij
e769f68613 armv8: semihosting: do not inline trap call
The semihosting trap call does not like being inlined, probably
because that will mean register reordering screwing up the return
value in r0, so tag this function "noinline".

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:45 -04:00