Commit graph

6473 commits

Author SHA1 Message Date
Kumar Gala
0f060c3bf8 85xx: Add basic e500mc core support
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.

* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:47 -05:00
Kumar Gala
a38a5b6edd 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
e500mc's 64-byte cacheline properly when it gets added.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:23 -05:00
Georg Schardt
5deb8022c3 ppc4xx: New board avnet fx12 minimodul
This patch adds support for the avnet fx12 minimodul.
It needs the "ppc4xx: Generic architecture for xilinx ppc405"
patch from Ricardo.

Signed-off-by: Georg Schardt <schardt@team-ctech.de>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:34:26 +02:00
Ricardo Ribalda Delgado
1f4d53260e ppc4xx: Generic architecture for xilinx ppc405(v3)
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.

Any custom xilinx ppc405 board can be added very easily with no code
duplicity.

This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h

This patch is prepared to work with the latest version of EDK (10.1)

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:26:09 +02:00
Stefan Roese
485c00a57f ppc4xx: Disable DDR2 autocalibration on Kilauea for now
Since the new autocalibration still has some problems on some Kilauea
boards with 200MHz DDR2 frequency we disable the autocalibration and
use the hardcoded values as done before. This seems to work reliably
on all known DDR2 frequencies.

After the autocalibration issue is fixed we will enable it again.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:25:13 +02:00
Wolfgang Denk
d9d8c7c696 Fix strmhz(): avoid printing negative fractions
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-22 08:52:19 +02:00
Richard Retanubun
4a7f6b750d mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig function
This is done to allow other 83XX based platforms which also have UPM
(e.g. 8360) to configure and use their UPM in u-boot.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:41:04 -05:00
Anton Vorontsov
3bf1be3c0c mpc83xx: add support for switching between USB Host/Function for MPC837XEMDS
With this patch u-boot can fixup the dr_mode and phy_type properties
for the Dual-Role USB controller.

While at it, also remove #ifdefs around includes, they are not needed.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:40:01 -05:00
Anton Vorontsov
b3379f3fd1 mpc83xx: add ELBC NAND support for the MPC837XEMDS boards
Though NAND chip is replaceable on the MPC837XE-MDS boards, the
current settings don't work with the default chip on the board.
Nevertheless Freescale's U-Boot sets the option register correctly,
so I just dumped the register from the working u-boot. My guess is
that the old settings were applicable for some pilot boards, not
found in the production.

This patch also enables FSL ELBC driver so that we could access
the NAND storage in the u-boot.

The NAND support costs about 45KB, so the u-boot no longer fits
into two 128KB NOR flash sectors, thus we also have to adjust
environment location: add another 128KB to the monitor length.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3,  you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.

Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
asserted upon access to the NAND chip, keep the default state.

Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:17 -05:00
Anton Vorontsov
00f7bbae92 mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB,
standalone or acting as a PCI agent. User's Guide says:

- When the CPLD recognizes its location on the PIB it automatically
  configures RCW to the PCI Host.
- If the CPLD fails to recognize its location then it is automatically
  configured as an Agent and the PCI is configured to an external arbiter.

This sounds good. Though in the standalone setup the CPLD sets PCI_HOST
flag (it's ok, we can't act as PCI agents since we receive CLKIN, not
PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without
any arbiter bad things will happen (here the board hangs during any config
space reads).

In this situation we must disable the PCI. And in case of anybody really
want to use an external arbiter, we provide "pci_external_aribter"
environment variable.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:14 -05:00
Anton Vorontsov
1da83a63d8 mpc83xx: add SGMII riser module support for the MPC8378E-MDS boards
This involves configuring the SerDes and fixing up the flags and
PHY addresses for the TSECs.

For Linux we also fix up the device tree.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:08 -05:00
Anton Vorontsov
e6d9c8916d mpc83xx: add TSECs' HRCWH masks for MPC837x processors
We'll use these masks to parse TSEC modes out of HRCWH.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:05 -05:00
Anton Vorontsov
6f9cc6608b mpc83xx: serdes: add forgotten shifts for rfcks
The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).

Though, for SGMII we'll need 125MHz clocks.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:01 -05:00
Anton Vorontsov
55c531984d mpc83xx: fix serdes setup for the MPC8378E boards
MPC837xE specs says that SerDes1 has:

— Two lanes running x1 SGMII at 1.25 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.

And for SerDes2:

— Two lanes running x1 PCI Express at 2.5 Gbps;
— One lane running x2 PCI Express at 2.5 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.

The spec also explicitly states that PEX options are not valid for
the SD1.

Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX,
which is wrong to do.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:33:25 -05:00
Anton Vorontsov
5c2ff323a9 mpc83xx: mpc8360emds: rework LBC SDRAM setup
Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes
it difficult to use (b/c then the memory is discontinuous and
there is quite big memory hole between the DDR/SDRAM regions).

This patch reworks LBC SDRAM setup so that now we dynamically
place the LBC SDRAM near the DDR (or at 0x0 if there isn't any
DDR memory).

With this patch we're able to:

- Boot without external DDR memory;
- Use most "DDR + SDRAM" setups without need to support for
  sparse/discontinuous memory model in the software.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:31:07 -05:00
Wolfgang Denk
def0819e92 FDT: don't use private kernel header files
On some systems (for example Fedora Core 4) U-Boot builds with the
following wanrings only:

...
In file included from /home/wd/git/u-boot/include/libfdt_env.h:33,
                 from fdt.c:51:
		 /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead!

This patch fixes this problem.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 21:35:44 +02:00
Wolfgang Denk
06c2942218 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-10-21 21:19:35 +02:00
Stefan Roese
f4d14c5550 ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setup
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Stefan Roese
43cbce69d4 ppc4xx: Correctly setup ranges property in ebc node
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Dirk Eibach
d7b26d5832 ppc4xx: Add GDSys neo 405EP board support
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Niklaus Giger
c11da19454 ppc4xx: Update configs for Netstal boards
I reorganized my config files, putting the common stuff into netstal-common.h
(got the idea by looking a amcc-common.h from Stefan).

Added stuff to boot the new powerpc linux via NFS (only tested with HCU4).

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:57 +02:00
Adam Graham
c9c11d751e ppc4xx: Add routine to retrieve CPU number
Provide a weak defined routine to retrieve the CPU number for
reference boards that have multiple CPU's.  Default behavior
is the existing single CPU print output.  Reference boards with
multiple CPU's need to provide a board specific routine.
See board/amcc/arches/arches.c for an example.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:56 +02:00
Adam Graham
59217bae40 ppc4xx: Add static support for 44x IBM SDRAM Controller
This patch add the capability to configure a PPC440 based IBM SDRAM
Controller with static, compiled-in, values. PPC440 memory subsystem
includes a Memory Queue core.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:51 +02:00
Adam Graham
f09f09d389 ppc4xx: Add AMCC Arches board support (dual 460GT)
The Arches Evaluation board is based on the AMCC 460GT SoC chip.
This board is a dual processor board with each processor providing
independent resources for Rapid IO, Gigabit Ethernet, and serial
communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
FLASH, UART, EEPROM and temperature sensor, along with a shared debug
port. The two 460GT's will communicate with each other via shared
memory, Gigabit Ethernet and x1 PCI-Express.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:46 +02:00
Stefan Roese
f61f1e150c Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-10-21 11:43:08 +02:00
Wolfgang Denk
055b12f2ff TQM8260: environment in flash instead EEPROM, baudrate 115k
Several customers have reported problems with the environment in
EEPROM, including corrupted content after board reset. Probably the
code to prevent I2C Enge Conditions is not working sufficiently.

We move the environment to flash now, which allows to have a backup
copy plus gives much faster boot times.

Also, change the default console initialization to 115200 bps as used
on most other boards.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:27:53 +02:00
Kumar Gala
1836881190 85xx: Fix compile warning in mpc8536ds.c
mpc8536ds.c: In function 'is_sata_supported':
mpc8536ds.c:615: warning: unused variable 'devdisr'

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-21 11:27:08 +02:00
Wolfgang Denk
8ed44d91c8 Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:25:39 +02:00
Wolfgang Denk
08ef89ecd1 Use strmhz() to format clock frequencies
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:25:38 +02:00
Wolfgang Denk
d50c7d4be1 strmhz(): Round numbers when printing clock frequencies
Round clock frequencies for printing.

Many boards printed off clock frequencies like 399 MHz instead of the
exact 400 MHz because numberes were not rounded. This is fixed now.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:25:35 +02:00
Timur Tabi
681c02d05b 85xx: properly document MPC85xx_PORDEVSR2_SEC_CFG
Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot
to add a comment that the correct value disagrees with the 8544 reference
manual.  The changelog for that commit is also wrong, as it says "bit 28"
when it should be "bit 24".

Signed-off-by: Timur Tabi <timur@freescale.com>
2008-10-21 11:15:20 +02:00
Markus Klotzbuecher
50bd0057ba Merge git://git.denx.de/u-boot into x1
Conflicts:

	drivers/usb/usb_ohci.c
2008-10-21 09:18:01 +02:00
Wolfgang Denk
f82642e338 Merge 'next' branch
Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-18 21:59:44 +02:00
Heiko Schocher
360fe71e82 mgcoge: add redundant environment sector
Signed-off-by: Heiko Schocher <hs@denx.de>
2008-10-18 21:54:08 +02:00
Heiko Schocher
53ebf0c470 mgsuvd: update size of environment
Signed-off-by: Heiko Schocher <hs@denx.de>
2008-10-18 21:54:08 +02:00
Jason Jin
2e26d837f1 Enabled the Freescale SGMII riser card on 8536DS
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-10-18 21:54:08 +02:00
Liu Yu
7e183cad0c Enabled the Freescale SGMII riser card on 8572DS
This patch based on Andy's work.
Including command 'pixis_set_sgmii' support.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
2008-10-18 21:54:07 +02:00
Liu Yu
bff188baf9 Make pixis_set_sgmii more general to support MPC85xx boards.
The pixis sgmii command depend on the FPGA support on the board, some 85xx
boards support SGMII riser card but did not support this command, define
CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command.

Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits
are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and
PIXIS_VCFGEN1_MASK in header file for both boards.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
2008-10-18 21:54:07 +02:00
Ed Swarthout
5e981d683d Add cpu/8xxx to TAGS_SUBDIRS
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18 21:54:05 +02:00
Ed Swarthout
e1f7d22b8b fsl_law clear enable before changing.
Debug sessions may have left enabled laws.
Changing lawbar with an unkown enabled tgtid could cause problems.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18 21:54:05 +02:00
Ed Swarthout
86be510f7b mpc8572 additional end-point mode
mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0.
Include host_agent == 0 decode for end-point determination.

This is not needed for the ds reference board since pcie3 will be a host
in order to connect to the uli chip.  Include it here as a reference for
other mpc8572 boards.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18 21:54:05 +02:00
Ed Swarthout
6856b3d022 85xx if NUM_CPUS>1, print cpu number
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18 21:54:05 +02:00
Ed Swarthout
f7fecc3e25 pixis do not print long help if not configured
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18 21:54:05 +02:00
Andy Fleming
0e17f02a8a Have u-boot pass stashing parameters into device tree
Some cores don't support ethernet stashing at all, and some
instances have errata.  Adds 3 properties to gianfar nodes
which support stashing.  For now, just add this support to
85xx SoCs.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-10-18 21:54:05 +02:00
Haiying Wang
c21617fd26 Add DDR options setting on MPC8641HPCN board
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:05 +02:00
Haiying Wang
4ca06607d6 Add ddr interleaving suppport for MPC8572DS board
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.

* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.

* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:05 +02:00
Haiying Wang
1f293b417a Add debug information for DDR controller registers
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:05 +02:00
Haiying Wang
c9ffd839b1 Check DDR interleaving mode
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:05 +02:00
Haiying Wang
dfb49108e4 Pass dimm parameters to populate populate controller options
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00
Haiying Wang
dbbbb3abef Make DDR interleaving mode work correctly
Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00