Commit graph

7 commits

Author SHA1 Message Date
Simon Glass
c60e6a24dd CI: x86: coreboot: Update to latest coreboot
Use a recent coreboot build for this test.

The coreboot commit is:

   6f5ead14b4 mb/google/nissa/var/joxer: Update eMMC DLL settings

This is build with default settings, i.e. QEMU x86 i440fx/piix4

Add some documentation as to how to update it next time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-17 12:29:21 -04:00
Simon Glass
d60fb7a958 x86: coreboot: Update doc for CBFS access
Add an example to show how cbfs is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[Removed CONFIG_CMD_CBFS from defconfig files]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Simon Glass
b6b33d104d x86: coreboot: Document how to enable the debug UART
This is not obvious so add a little note about how it works.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
984639039f Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-31 11:01:31 -04:00
Simon Glass
e74d0ec80b x86: coreboot: Document the memory map
Add information about memory usage when U-Boot is started from coreboot.
This is useful when debugging. Also, since coreboot takes a chunk of
memory in the middle of SDRAM for use by PCI devices, it can help avoid
overwriting this with a loaded kernel by accident.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15 19:50:23 +08:00
Simon Glass
538437ed39 x86: Add a 64-bit 'coreboot64' build
Coreboot is a first-stage bootloader mostly used on x86 devices as an
alternative to UEFI. Coreboot runs in 32-bit mode.

U-Boot currently supports booting from coreboot as a second-stage
bootloader, also in 32-bit mode. However it is useful to be able to run
U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
over the CPU and jumps to a 64-bit U-Boot proper.

Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.

This allows running 64-bit EFI images on x86, for example, without needing
a native U-Boot port for a board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04 15:28:28 +08:00
Bin Meng
a856e934ca doc: board: Add coreboot board doc
This extracts coreboot board specific information from README.x86,
converts plain text documentation to reST format and adds it to
Sphinx TOC tree. No essential content change.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-24 10:07:24 -04:00