The value CONFIG_ALTERA_SPI_IDLE_VAL is never re-defined by a board.
Rename this to ALTERA_SPI_IDLE_VAL.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Import linux commit 007773e16a6f ("spi: nxp-fspi: Ensure width is
respected in spi-mem operations") to fix SPI access on boards which
don't have all SPI I/O lines connected to the flash.
Since commit 71025f013c ("mtd: spi-nor-core: Rework hwcaps selection")
u-boot figures out the capabilities by looking at spi_mem_supports_op().
The FlexSPI driver doesn't take the board layout into account. Fix that.
Fixes: 383fded70c ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When slave drivers don't set the max_read_size, the spi-mem should
directly use data.nbytes and not limit to any size. But current
logic will limit to the max_write_size.
This commit mirrors the same changes in the dm version done in
commit 535b1fdb8e ("spi: spi-mem: Fix read data size issue").
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Since commit 43c145b8b3 ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
(in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller
in software sequencer mode.
ICH controller can only transfer a small number of bytes at once.
Before commit 43c145b8b3, the logic happens to make sure data.nbytes
is limited to slave->max_write_size but after commit 43c145b8b3
data.nbytes is no longer limited because slave->max_read_size is not
initialized with a valid number.
Fixes: 43c145b8b3 ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When booting from coreboot we may not have a PCH driver available. The
SPI driver can operate without the PCH but currently complains in this
case. Update it to continue to work normally. The only missing feature
is memory-mapping of SPI-flash contents, which is not essential.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The driver depends on DM_SPI and if it's not available (e. g. in SPL),
then we should not try to build it as this will fail.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Define LOG_CATEGORY for all uclass to allow filtering with
log command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The spi_get_bus_and_cs() may be called on the same bus and chipselect
with different frequency or mode. This is valid usecase, but the code
fails to notify the controller of such a configuration change. Call
spi_set_speed_mode() in case bus frequency or bus mode changed to let
the controller update the configuration.
The problem can easily be triggered using the sspi command:
=> sspi 0:0@1000
=> sspi 0:0@2000
Without this patch, both transfers happen at 1000 Hz. With this patch,
the later transfer happens correctly at 2000 Hz.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.
Rework the hwcaps selection logic to use spi_mem_supports_op().
To make sure the build doesn't break for boards not using CONFIG_DM_SPI,
add a simple SPI_{RX,TX}_ based hwcaps selection logic in spi-mem-nodm
similar to spi_mem_default_supports_op(). This change is only
compile-tested.
To avoid SPL size problems on the x530 board, the old hwcaps selection
is still kept around. Leaving the code in-place was getting difficult to
read and understand, so the code is restructured to have it all in one
isolated function. As a result of this, the parameter hwcaps to
spi_nor_setup() is no longer needed. Remove it.
Based on the Linux commit c76f5089796a (mtd: spi-nor: Rework hwcaps
selection for the spi-mem case, 2019-08-06)
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can not use
automatic write completion polling in DTR mode. Further, no write
completion polling makes it impossible to use DAC mode for DTR writes.
In that mode, the controller does not know beforehand how long a write
will be and so it can de-assert Chip Select (CS#) at any time. Once CS#
is de-assert, the flash will go into burning phase. But since the
controller does not do write completion polling, it does not know when
the flash is busy and might send in writes while the flash is not ready.
So, disable write completion polling and make writes go through indirect
mode for DTR writes and let spi-mem take care of polling the SR.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.
This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It needs a read delay of 4 in
octal DTR mode. But since the calibration procedure is run before the
flash is switched in octal DTR mode, it yields a read delay of 2. A
value of 4 works for both octal DTR and legacy modes.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.
This means that controller drivers that want to support DTR mode can't
use spi_mem_default_supports_op(). Driver authors have to roll their own
supports_op() function and mimic the buswidth checks. Or even worse,
driver authors might skip it completely or get it wrong.
Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.
So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.
All usages of sizeof(op->cmd.opcode) also need to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add a driver for Macronix SPI controller IP.
This patch referred from linux spi-mxic.c. The difference from the
linux version is described here.
1. To adapt uboot spi framework, modify some functions naming.
2. Remove the incompatible functions of Uboot.
3. Add dummy byte recalculattion function to support dummy buswidth
not align data buswidth operation.(ex: 1-1-4, 1-1-8)
4. Add Octal mode support.
Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: fixed file permission, comment line, kconfig]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
TCF flag only means that all data was sent to FIFO. To check if the
data was sent out of FIFO we should also wait for the BUSY flag to be
cleared. Otherwise there is a race condition which can lead to
inability to write short (one byte long) data.
Signed-off-by: Daniil Stas <daniil.stas@posteo.net>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Enable manual start in zynqmp_qspi_fill_gen_fifo().
Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of
GQSPI_IXR_GFEMTY_MASK.
Add dummy write to genfifo register in chipselect.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2
("spi: kirkwood: prevent configuring speed exceeding max controller freq")
the spi frequency could be set to 0 on platform where spi-max-frequency
is not defined (e.g. on armada-388-gp). Prevent limiting speed in
mentioned cases.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Marcin Wojtas <marcin@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds a limitation in the kirkwood_spi driver
set_speed hook, which prevents setting too high transfer
speed.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.
Modify the baud rate calculation to handle these differences for the
Armada case. Potentially a baud rate can be setup using a number of
different pre-scalar and scalar combinations. This code tries all
possible pre-scalar divisors (8 in total) to try and find the most
accurate set.
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Adding timeout mechanism to avoid spi driver from stucking
in the while loop in __atcspi200_spi_xfer().
Signed-off-by: Dylan Jhong <dylan@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Use __func__ instead for function name in debug.
Use Linux style u32 instead of uint32_t.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In case of reading large area and memory-map mode is misconfigured
(memory-map size declared lower than the real size of the memory chip)
watchdog can be triggered.
Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it.
Issue reproduced with stm32mp157c-ev1 board and memory map size set to
1, with following command:
sf read 0xC0000000 0 0x4000000
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set. When checking for errors, it only
checks that it is not NULL. Since positive numbers are not errors,
only check for negative numbers when handling errors.
Fixes: 383fded70c ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The set_speed() callback should configure the bus speed, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
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Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.04-rc3
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
If zynqmp_qspi_set_speed() is called multiple times with the same speed,
then on the second call it will skip recalculating the baud_rate_val as
it assumes the speed is already configured correctly. But it will still
write the baud_rate_val to the configuration register and call
zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the
baud_rate_val, it will use the initial value of 0 . This causes the
driver to run at maximum speed which for many spi flashes is too fast and
causes data corruption.
Instead only write out a new baud_rate_val if we have calculated the
correct baud_rate_val.
This opens up another issue with the "if (speed == 0)", we don't save
off the new plat->speed_hz value when setting the baud rate on the
speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and
have speed==0 just use the same calculation as a normal speed. That will
cause the baud_rate_val to use the slowest speed possible, which is the
safest option.
Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com>
CC: jagan@amarulasolutions.com
CC: michal.simek@xilinx.com
CC: Ashok Reddy Soma <ashokred@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c11 ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL
workaround as the LS208x and also has a 64 byte TX buffer.
With the previous settings SPI-NAND reads over AHB were
corrupted.
Fixes: 91afd36f38 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API")
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Adapted from kernel commit b0177aca7aea
From: Michael Walle <michael@walle.cc>
Make use of a core helper to ensure the desired width is respected
when calling spi-mem operators.
Otherwise only the SPI controller will be matched with the flash chip,
which might lead to wrong widths. Also consider the width specified by
the user in the device tree.
Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller")
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot]
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It
also doesn't allow the zynqmp_gqspi driver to calculate the correct
number of dummy cycles for some NOR ops (as doing so also requires the
buswidth).
Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us
the buswidth values to correctly support all SNOR_PROTO_X_X_X commands
and to properly calculate dummy cycles.
Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com>
CC: jagan@amarulasolutions.com
CC: michal.simek@xilinx.com
CC: Ashok Reddy Soma <ashokred@xilinx.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds support for MTK SPI NOR controller, which you
can see on mt7622 & mt7629.
1. This controller is designed only for SPI NOR. We can't adjust
its bus clock dynamically. Set clock in dts instead.
2. This controller only supports 1-1-1 write mode.
3. Remove mtk_snor_match_read() since upper SPI-MEM layer already
handles command.
4. sf read/write/update commands are tested with this driver.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
This patch adds spi controller support for MediaTek MT7620 SoC.
The SPI controller supports two chip selects. These two chip selects are
implemented as two separate register groups, but they share the same bus
(DI/DO/CLK), only CS pins are dedicated for each register group.
Appearently these two register groups cannot operates simulataneously so
they are implemented as one controller.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
In case the clock framework is enabled, enable the SPI controller clock
and obtain max frequency from the clock framework.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
