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3 commits

Author SHA1 Message Date
York Sun
316f0d0f8f powerpc: mpc85xx: Fix static TLB table for SDRAM 
Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.

Signed-off-by: York Sun <york.sun@nxp.com>
 2017-12-06 14:54:12 -08:00
York Sun
3aab0cd852 powerpc/mpc85xx: Cleanup license header in source files 
Fix the license header introduced by the following patches

Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board

Signed-off-by: York Sun <yorksun@freescale.com>
 2013-08-12 15:04:24 -07:00
Xie Xiaobo
49f5befafd powerpc/85xx: Add TWR-P10xx board support 
TWR-P1025 Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (on board DDR)
   64Mbyte 16bit NOR flash
   One microSD Card slot

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC3: Connected to Atheros AR8035 GETH PHY

UART:
   Two UARTs are routed to the FDTI dual USB to RS232 convertor

USB: Two USB2.0 Type A ports

I2C:
   AT24C01B 1K Board EEPROM (8 bit address)

QUICC Engine:
   Connected to DP83849i PHY supply two 10/100M ethernet ports
   QE UART for RS485 or RS232

PCIE:
   One mini-PCIE slot

Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: York Sun <yorksun@freescale.com>
 2013-08-09 12:41:25 -07:00