Its possible that k3_avs_priv is NULL because the driver may not have
been probed yet. Therefore check if pointer is valid before
dereferencing it.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
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Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
- Move P2SB from Apollo Lake to a more generic location
- Add a function to find a device by drvdata in DM core
- Enhancement of DM IRQ uclass driver
- Add a clock driver for Intel devices
- Add support for ACPI general-purpose events
- Add a TPM driver for H1/Cr50
- Enable TPM on Google Chromebook Coral
Set the correct offset length and chip address offset mask for each
device to allow correct access to total capacity of the devices.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
At present driver model supports the IRQ uclass but there is no way to
request a particular interrupt for a driver.
Add a mechanism, similar to clock and reset, to read the interrupts
required by a device from the device tree and to request those interrupts.
U-Boot itself does not have interrupt-driven handlers, so just provide a
means to read and clear an interrupt. This can be useful to handle
peripherals which must use an interrupt to determine when data is
available, for example.
Bring over the basic binding file as well, from Linux v5.4. Note that the
older binding is not supported in U-Boot; the newer 'special form' must be
used.
Add a simple test of the new functionality.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There can be different types of interrupt controllers in a system and some
drivers may need to distinguish between these. In general this can be
handled using the device tree by adding the interrupt information to
device nodes.
However on x86 devices we have interrupt controllers which are not tied
to any particular device and not really used in U-Boot. These still need
to be inited, so a convenient method is to give each controller a type
and allow a particular controller type to be probed.
Add support for this in sandbox along with a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove the new bland line at EOF of test/dm/irq.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Now that we can use direct access to the system malloc() in sandbox, drop
the remaining uses of os_malloc().
The only one remaining now is for the RAM buffer, which we do want to be
at a known address, so this is intended.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.
Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
At present this method uses a non-const udevice pointer, but the call
should not modify the device. Use a const pointer.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
Add ability to query size of eeprom device and partitions
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.
Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.
Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.
This adds a uclass and enables it for sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Chromium EC commands can be up to 16-bits, so using a uint8_t here can
cause truncation. Update to use a uint instead.
It looks like this should likely have been done as a part of
9fea76f5d3, but this function was skipped
for some reason.
Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
These functions do not use driver model but are still used. Move them to a
new eeprom.h header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Drop inclusion of crc.h in common.h and use the correct header directly
instead.
With this we can drop the conflicting definition in fw_env.h and rely on
the crc.h header, which is already included.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are a few whitespace problems with this code. Tidy them up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is only used by a few files so it should not be in the common header.
Move it out.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
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Merge tag 'u-boot-imx-20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191105
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
j721e SoCs have different OPP tables. Add support for the same.
Note: DM Still has lot of voltages TBD hence the correct
values need to be programmed once they are published.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
clk and pinctrl will be get(probed) during each device probe,
we don't need to probe them in scu driver. Only need to bind the sub-nodes
(clk and iomuxc) of MU node with their drivers.
So drop the code to probe the clk/pinctrl, and this patch will make it
easy to add more subnodes.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ,
so update the interface to add new argument.
Signed-off-by: Ye Li <ye.li@nxp.com>
[agust: fixed imx8m-power-domain build]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add sc_pm_is_partition_started to check whether a partition
has been started. This will be used to detect M4 partition booted up or
not, then we could choose which dtb to use. If M4 is up, we need
use dtb, such as imx8qm-mek-rpmsg.dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove inclusion of <asm/test.h> in pci_sandbox.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This function is useful in PCI emulators. More it into the header file to
avoid duplicating it in other drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This method is not used anymore since the bus/device/function of PCI
devices can be obtained from their (parent's per-child) platform data.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some functions and a struct should be marked static since they are not
used outside this file. Update them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Rename this ID to SANDBOX_PCI_SWAP_CASE_EMUL_ID since it is more
descriptive and allows us to add new PCI emulators without any conflict or
confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The RCC driver have no operation so the new NOP uclass
is more appropriate. It only used as parent for clock and reset driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Use MISC u-class to export the NVM register (starting at 0xF8 offset)
and avoid specific API.
- SHADOW have offset < 0.
- NVM have register > 0
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Since the commit 8729b1ae2c ("misc: Update read() and
write() methods to return bytes xfered"); The misc bsec driver
need to be adapted to reflect the number of transferred bytes.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
