Commit graph

36 commits

Author SHA1 Message Date
Masahiro Yamada
b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
0914011310 command: Remove the cmd_tbl_t typedef
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.

Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.

This requires quite a few header-file additions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 18:36:55 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
4d72caa5b9 common: Drop image.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
90526e9fba common: Drop net.h from common header
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:31 -04:00
Madalin Bucur
6eb32a03e0 driver: net: fm: add DM ETH support
Probe the FMan MACs based on the device tree while
retaining the legacy code/functionality.
One notable change introduced here is that, for DM_ETH,
the name of the interfaces is corrected to the fmX-macY
format, that avoids the referral to the MAC block names
which were incorrect for FMan v3 devices (i.e. DTSEC,
TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1).
The legacy code is left unchanged in this respect.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Yuantian Tang
35ad8f7af4 armv8: ls1046ardb: update the DIMM WRLVL_START value
The WRLVL_START values are optimized for old DDR MTA18ASF1G72AZ.
Update DDR struct to set new WRLVL_START values so that the new DIMM
MTA18ADF2G72AZ get optimized and the old DIMM still works.

Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 17:46:46 +05:30
Udit Agarwal
5536c3c9d0 freescale/layerscape: Rename the config CONFIG_SECURE_BOOT name
Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict
with UEFI secure boot.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 16:32:08 +05:30
Tom Rini
d94604d558 Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEorkTmaQ1QAtDiYw67UVZlNoLnbQFAlwOzFoACgkQ7UVZlNoL
 nbQUdQ//SRRBfjUe8RYTbojvTGQav0GTxnMkz4GFSrqu0nvGMW2YSlheOMqq72sg
 rK5mQqDvdkItCn+G8AZ5NV2ijkQ7NQWCfqL3EtApzTpv6qjfgv7xvopz8q4NZvzB
 Wp+4cFf9YQjNwhJ7kLvWHB7SBiz9AfMYRAj9cscH9xsGL3HxPj62WDfwyK/QXana
 KIxRKQ26/1AdOZy272yv70vlFj4IwForxV3ACimsWRuYcb8yre3pE0tD7XpMCSNv
 9GOfL7r4LS7U0+QnJoVeYLMhttRvOGJNUYtO2+ImO5NC3u9v8ehYEQ3FjGmM69CB
 vuPDQBDQc+Ap+Iu3k18PYSstp+mc9fbe9SQdlx6ARAecQqWTN4EOhf8s3m2bQq3S
 B58I0Zvowcdm8V2JKdXw94UqZX862U8PWH0BmcuX+4k+kRDwwU4XQY2nLp+Htz1w
 2q6vEdKGj7YUOaomx9fmKRL+9BFGoD+M9mTiHOwzqwxy6Pa9VkruSvMErM7p2l/z
 xI/Q+xPJhyk5TXgZRsz4Nat59WpifWruibKEd4PArQ446heHWmzLWjw/MWiFyd/H
 agCdpDZVJ8R7h1Krs+Ez8XjR1Qcg0gs+CdNBuvqxzOpMQGGonXA1nwi8YfHykhII
 urfoC8pew1yxiLGw7J2JSX808HV/09WCSEsrOOhE3T78rXTDlS4=
 =aT7d
 -----END PGP SIGNATURE-----

Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-10 17:19:59 -05:00
Rajesh Bhagat
8e156bb176 armv8: ls1046ardb: Add TFABOOT support
TFABOOT support includes:
 - ls1046ardb_tfa_defconfig to be loaded by trusted firmware
 - environment address and size changes for TFABOOT
 - FMAN address changes for TFABOOT
 - define BOOTCOMMAND for TFABOOT

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-12-06 14:37:19 -08:00
Laurentiu Tudor
3cb4fe65f9 armv8: ls1046a: initial icid setup support
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:33 -07:00
Tom Rini
781e8f6cb1 ls1046ardb: Add qspi_spl variant to the MAINTAINERS file
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-31 14:53:18 -04:00
York Sun
038b965c2b armv8: ls1046ardb: Add falcon mode for for QSPI boot
A new defconfig is introduced to support SPL boot from QSPI NOR
flash. This is to support falcon mode for faster booting into
Linux.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 11:51:23 -07:00
Bhaskar Upadhaya
7191d45348 board: Kconfig: Re-Arrangement of PPA firmware and header addresses
PPA firmware and header address may vary depending upon different
boards, configure ppa firmware and header address in board specific
Kconfig.

Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-06-08 16:43:19 -07:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
York Sun
f513de6c82 armv8: ls1046ardb: Add RDIMM support
This adds 2Rx8 RDIMM on LS1046ARDB board. Tested with RDIMM
MTA18ASF2G72PDZ and MTA9ASF1G72PZ.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30 09:14:07 -08:00
Prabhakar Kushwaha
4ace304062 boards: ls1046ardb: disable unavailable "ethernet" node in dts
Linux device tree contains "ethernet" node for all possible
interface supported by SoC i.e. LS1046A.

It is not necessary for a SerDes protocol to support all possible
interface. So disable unavailable "ethernet" node in device tree.

Also, enable FDT_SEQ_MACADDR_FROM_ENV to fetch MAC address
sequentially from environment variables

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-24 12:42:50 -07:00
Hou Zhiqiang
e4b5143eb6 fsl-lsch2: csu: remove multiple calling function
Function enable_layerscape_ns_access() is alreayd called soc-wide.
Remove duplicated calling from individual boards.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Add commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Qianyu Gong
3016084b38 armv8: ls1046ardb: update core frequency to 1800MHZ
Update the default core frequency to 1800MHZ for best performance under
SD boot and eMMC boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:11:34 -07:00
Simon Glass
6e2941d787 common: freescale: Move arch-specific declarations
The declarations should not be in common.h. Move them to the arch-specific
headers.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05 12:30:55 -04:00
Alison Wang
8104deb2d6 armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1046A
This patch is to adjust the memory mapping for FLash/SD card on
LS1046AQDS and LS1046ARDB, such as FMAN firmware load address, U-Boot
start address on serial flash and environment address.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23 09:51:28 -07:00
York Sun
99b47c25d0 armv8: ls1046ardb: Make NET independent of FMan
This allows using PCIe NIC without enabling DPAA FMan.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: Mingkai Hu <mingkai.hu@nxp.com>
2017-05-23 09:23:52 -07:00
York Sun
fedebf0d08 armv8: layerscape: Fix DDR size calcuation for SPL build
Commit 088454cd dropped return value from initram(), setting
gd->ram_size directly. Three boards were missed for SPL boot.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-24 09:07:12 -07:00
Ruchika Gupta
511fc86d0b arm: ls1046ardb: Add SD secure boot target
- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main
  U-Boot by SPL to also include the u-boot Secure Boot header size
  as header is appended to u-boot image. So header will also be
  copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
  (128K) where 32K are reserved for use by boot ROM and 6K for the
  header.
- Reduce the size of CAAM driver for SPL Blobification functions
  and descriptors, that are not required at the time of SPL are
  disabled. Further error code conversion to strings is disabled
  for SPL build.

Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17 09:03:30 -07:00
Vinitha Pillai-B57223
f7244f2c48 armv8: LS1046ARDB: Add QSPI Secure Boot target
Add QSPI Secure Boot target. Also enable sec init.

Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17 09:03:30 -07:00
Sumit Garg
a52ff334c5 armv8: ls1046ardb: SPL size reduction
Using changes in this patch we were able to reduce approx 4k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1046ardb/Makefile to remove
   compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1046ardb/ls1046ardb.c to keep
   only ddr_init and board_early_init_f funcations in case of SPL
   build.
3. Changes in ls1046a_common.h & ls1046ardb.h to remove driver
   specific macros due to which static data was being compiled in
   case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
   build and NAND driver from bieng compiled in case of SPL MMC build.

Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17 09:03:30 -07:00
Simon Glass
3eace37e50 arm: freescale: Rename initdram() to fsl_initdram()
This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-12 13:28:32 -04:00
Simon Glass
088454cde2 board_f: Drop return value from initdram()
At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05 13:59:20 -04:00
Simon Glass
52c411805c board_f: Drop board_type parameter from initdram()
It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05 13:58:44 -04:00
York Sun
4961eafc25 armv8: layerscape: Update early MMU for DDR after initialization
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
York Sun
36cc0de0b9 armv8: layerscape: Rewrite memory reservation
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
Hou Zhiqiang
dccef2ec01 ls1046ardb: Add support power initialization
Add the chip power supply voltage initialization on LS1046ARDB.
Add function power_init_board(), and it will initialize the
PMIC and call the chip power initialization function.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:29:13 -08:00
Hou Zhiqiang
6424577b1b ls1046ardb: cpld: add API for selecting core volt
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:29:02 -08:00
Shengzhou Liu
90101386f1 fsl/board/ddr: optimize board-specific cpo for erratum A-009942
Optimize board-specific cpo for erratum A-009942 on b4860qds,
ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb,
t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb,
t4qds, t4rdb boards.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-15 11:56:39 -08:00
Mingkai Hu
dd02936f81 armv8: ls1046ardb: Add LS1046ARDB board support
LS1046ARDB Specification:
-------------------------
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
	 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:11:00 -07:00