Commit graph

8447 commits

Author SHA1 Message Date
Simon Glass
d1de41d7fa exynos: Add support for spring
Spring is the first ARM-based HP Chromebook 11. It is similar to snow
and it uses the same Samsung Exynos5250 chip. But has some unusual
features. Mainline support for it has lagged snow (both in kernel and
U-Boot). Now that the exynos5 code is common we can support spring just
by adding a device tree and a few lines of configuration.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:17 -06:00
Simon Glass
68964dbc83 video: Remove the old parade driver
We have a new one which uses driver model and device tree configuration.
Remove the old one.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:16 -06:00
Simon Glass
05bccbcd76 power: Remove old TPS65090 drivers
Remove the old drivers (both the normal one and the cros_ec one) now that
we have new drivers that use driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:16 -06:00
Simon Glass
54abb000e3 exynos: Drop old exynos5250-specific board code
Now that most exynos5250 boards can use the generic exynos5 code, switch
over to it and remove the old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:16 -06:00
Simon Glass
c51212332a exynos: Drop old exynos5420-specific board code
Now that exynos5420 boards can use the generic exynos5 code, switch over to
it and remove the old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
2015-08-05 21:06:16 -06:00
Simon Glass
bf637ea5e4 exynos: config: Move common options to the common headers and tidy up
Many options are duplicated on the exynos5 boards. Move these to the common
files. Also some options are not used so can be removed.

Tidy this up to make the files easier to maintain.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
2015-08-05 21:06:16 -06:00
Simon Glass
d4061aa0e9 exynos: Enable new features for exynos5 boards
Enable PMICs, regulators and the like so that new drivers will be made
available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:15 -06:00
Stephen Warren
a5325cd5e9 configs: Remove CONFIG_SERIAL_MULTI
This config option isn't used anywhere at all. Remove all places that
define/enable the option.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-08-05 14:12:42 -04:00
Tom Rini
1a2728ae4f Merge git://git.denx.de/u-boot-x86 2015-08-05 14:12:37 -04:00
Paul Kocialkowski
b21144eb76 sunxi: MUSB gadget config provisions, with fastboot and USB mass storage support
This adds some config options to the sunxi-common config to enable the USB
download gadget and the fastboot and USB mass storage functions.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-08-05 17:20:34 +02:00
Paul Kocialkowski
2582ca0d80 sunxi: config update to stick with Kconfig changes
Now that some things were updated in Kconfig, they should be reflected on the
sunxi-common config too.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-08-05 17:20:34 +02:00
Paul Kocialkowski
95de1e2f26 usb: musb-new: CONFIG_MUSB prefix replacement with CONFIG_USB_MUSB
USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-08-05 17:20:34 +02:00
Ben Stoltz
cd326a32c9 x86: Add definitions for the x86-efi board and plumb it in
Add configuration and Kconfig changes for this board.

Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
82bc22ac8f x86: minnowmax: Drop the old PCI settings
These are now in the device tree so we don't need to use the CONFIG options.
Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:42 -06:00
Simon Glass
1f2be4cea4 x86: Drop CONFIG_DCACHE_RAM_MRC_VAR_SIZE from header file
This is provided in Kconfig so we don't need it here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:42 -06:00
Simon Glass
dcfe4a54ed x86: Move CONFIG_X86_SERIAL to Kconfig
Move this config option to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:42 -06:00
Simon Glass
ca4435ef28 x86: Move Chrome OS options to defconfig
Drop these from the header file and use Kconfig instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:42 -06:00
Bin Meng
fe3fbd3024 x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
9b911bed78 x86: Add Intel Bayley Bay board support
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
456ee909d6 x86: minnowmax: Remove smsc47x superio codes
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Tom Rini
e22b1a5494 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-08-04 12:21:45 -04:00
Vitaly Andrianov
8889e98415 configs: ti_armv7_keystone2: replace addr_uboot with loadaddr
This patch replaces not existing addr_uboot environment variable by
loadaddr at get_uboot_net and burn_uboot_xxx commands. Otherwise these
commands are broken.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
2015-08-03 15:58:37 -04:00
Nikhil Badola
e16b604ecf armv8/ls2085ardb: Add USB support for ls2085ardb
Add USB XHCI support for ls2085rdb platform

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:39 -07:00
Nikhil Badola
94e8cd805b armv8/ls2085aqds: Add USB support for ls2085aqds
Add USB XHCI support for ls2085qds platform

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:39 -07:00
Tang Yuantian
99e1bd4241 armv7/ls1021atwr: added deep sleep support in uboot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
gaurav rana
562583deb3 armv7/lS1021atwr: Enable bootscript for secure boot
Enable bootscript support in secure boot for establishing
chain of trust on LS1021atwr.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
Zhuoyu Zhang
5b72524246 armv7/ls1021a: Reserve secure code into RAM instead of OCRAM
For ls1021a, Reserve secure code in to memory in case OCRAM
is needed by other usage.

Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
Tom Rini
7a1af7a79b Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-08-02 07:40:37 -04:00
Peng Fan
f0ff57b0b2 imx: mx6ul_14x14_evk add basic board support
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
   supports sd for usdhc2, but can do hardware rework to make usdhc2 support
   emmc.

Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device
 Reset cause: POR
 Board: MX6UL 14x14 EVK
 I2C:   ready
 DRAM:  512 MiB
 MMC:   FSL_SDHC: 0, FSL_SDHC: 1
 *** Warning - bad CRC, using default environment

 In:    serial
 Out:   serial
 Err:   serial
 Net:   CPU Net Initialization Failed
 No ethernet found.
 Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:09 +02:00
Peng Fan
6f4b65eda9 imx: imx6_spl add mx6ul support
i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use
same address with i.MX6SX.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:09 +02:00
Peng Fan
94bd1d1430 mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL
DRAM space starts from 0x80000000 for i.MX6UL, so need to
fix LOADADDR, SYS_TEXT_BASE.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:08 +02:00
Peng Fan
436cf40f05 imx: mx6ul remove errata for i.MX6UL
Since i.MX6UL use A7 core, but not A9 core, we do not need
the erratas for i.MX6UL.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:07 +02:00
Nikita Kiryanov
d5af92315b sf: kconfig: add kconfig options for spi flashes
Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig.

Cc: Jagan Teki <jteki@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-08-02 10:51:39 +02:00
Nikita Kiryanov
b2f2eea0a7 usb: kconfig: usb keyboard kconfig
Add Kconfig options for USB keyboard and use them for cm-fx6.

Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-08-02 10:51:39 +02:00
Nikita Kiryanov
919e802c86 arm: mx6: usb: kconfig: add USB_EHCI_MX6 kconfig option
Add USB_EHCI_MX6 option to menuconfig and use it when migrating cm-fx6 usb
config to defconfig.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-08-02 10:51:39 +02:00
Nikita Kiryanov
7d731e3a9a arm: mx6: cm-fx6: move CMD configs to defconfig
Move CONFIG_CMD_* options that can be selected in menuconfig to cm-fx6
defconfig.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-08-02 10:51:37 +02:00
Nikita Kiryanov
4377859aa6 arm: mx6: cm-fx6: make it possible to not init display
Implement a cm-fx6 specific board_video_skip() to provide the option to not
initialize the display.

The new function does not init display if the environment variable "panel" is
not defined, or if it is set to an unsupported value.

Collateral changes:
- Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific).
- Don't use detect_hdmi(), since env controlled init makes it unnecessary.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2015-08-02 10:51:37 +02:00
Peng Fan
361b715bbf imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
   and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)

CPU:   Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  0 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-08-02 10:47:52 +02:00
Peng Fan
e6fc8995d6 imx: mx6sabresd/sabreauto runtime setting fdt_file
Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.

Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:47:05 +02:00
Tom Rini
8968b914be Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-07-31 20:16:21 -04:00
Shengzhou Liu
ff7ea2d18b powerpc/t1023rdb: add support for T1023RDB RevC
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Aneesh Bansal
5050f6f0e5 powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Aneesh Bansal
467a40dfe3 powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Tom Rini
cc35734358 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-07-29 18:58:39 -04:00
Jaiprakash Singh
7842950f7c powerpc/T102xRDB: Enable ifc nand ecc encode and decode
IFC nand ecc encode and decode mode are not correctly
set in CSOR register during nand initialization.Enable
ecc encode/decode in 4-bit mode

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:16 -07:00
Priyanka Jain
4b6067ae9d powerpc/T104xD4RDB: Add T104xD4RDB boards support
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
    T1040D4RDB is re-designed T1040RDB board with following changes :
    - Support of DDR4 memory
    - Support of 0x66 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 1 SGMII on DTSEC3
    - Support of QE-TDM

    Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
    SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
    - Support of DDR4 memory
    - Support for 0x86 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
    - Support of DIU

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:40:57 -07:00
Tom Warren
873e3ef90b T210: Add support for 64-bit T210-based P2571 board
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.

With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).

Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28 10:30:20 -07:00
Tom Warren
7aaa5a60ce ARM: Tegra210: Add support to common Tegra source/config files
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:20 -07:00
Thierry Reding
f41f0a1918 ARM: tegra: Use architected timer on ARMv8
ARMv8 requires an architected timer to be present, so it can be used
instead of the Tegra US timer. This allows for better code reuse.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28 10:30:18 -07:00
Thierry Reding
6527268d6e ARM: tegra: Disable SPL and non-cached memory on 64-bit
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:18 -07:00