Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.
Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.
Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.
Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.
Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG
information.
If this data is not present, the kernel misconfigures the TZIC, which results in
the timer interrupt handler never being called, so the kernel deadlocks while
calibrating its delay.
Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Define ARCH_MXC for i.MX devices. This is useful to identify features or
behaviors common to all i.MX SoCs.
The i.MX28 is omitted because its architecture is a bit different (like imx/mxc
vs. mxs in Linux).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
This is useful for forcing the ROM's
usb downloader to activate upon a watchdog reset.
Or, you can boot from either SD Card.
Currently, support added for MX53 and MX6Q
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Note: MX53 support untested.
Acked-by: Stefano Babic <sbabic@denx.de>
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.
The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.
Suggested-by: Yu Li <yk@magniel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU
Introduce two new macros to control conditional setup
MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
The serial driver for iMX SOCs is continuosly changed if a
new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port>
defines were used only to find the base address for the selected UART.
Instead of that, move the base address to the board configuration
file and drop all #ifdef from driver.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Helmut Raiger <helmut.raiger@hale.at>
CC: John Rigby <jcrigby@gmail.com>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
The PLL decoding algorithm didn't take into account many configuration bits.
Adjust it according to Linux kernel. Also, add PLL4 for MX53.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Hui <jason.hui@linaro.org>
Tested-by: Jason Liu <Jason.hui@linaro.org>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
This is a port of the official PLL errata workaround from Freescale to
mainline u-boot.
The PLL's in the i.MX51 processor can go out of lock due to a metastable
condition in an analog flip-flop when used at high frequencies.
This workaround implements an undocumented feature in the PLL (dither
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.
Signed-off-by: David Jander <david@protonic.nl>
On i.MX5, the asm-offsets.h file is not yet generated as it should be.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Add initial support for Freescale MX53 processor,
- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro
Signed-off-by: Jason Liu <r64343@freescale.com>
The patch is to support getting FEC MAC address from fuse bank.
Signed-off-by: Jason Liu <r64343@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
This patch is to fix build breakage and support new relocation
scheme for mx51evk.
- Correct IRAM base address and add size definition
The IRAM starts from 0x1FFE0000 on final revsion i.mx51 than
0x1FFE8000 which is for older revision.
- Include imx-regs.h in mx51evk.h
Definitions like CSD0_BASE_ADDR and IRAM_BASE_ADDR can be
referred to.
- Define CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
They are used to define init RAM layout.
- Remove comment for CONFIG_SYS_GBL_DATA_SIZE which has been
buried by Wolfgang's commit below
25ddd1fb: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value
Signed-off-by: Shawn Guo <shawn.gsc@gmail.com>
