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8 commits

Author SHA1 Message Date
Thomas Skibo
c0ffc12a70 riscv: Enable SPI flash env for SiFive Unmatched. 
Enable saving environment to SPI flash memory on SiFive
Unmatched.

Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2021-12-02 16:43:56 +08:00
Zong Li
835210a125 board: sifive: use ccache driver instead of helper function 
Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
 2021-09-07 10:34:29 +08:00
Zong Li
662e300bc0 riscv: cpu: fu740: Fix typo of date 
Fixed the typo of date of copyright declaration.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 2021-08-17 19:28:37 +08:00
Simon Glass
975e7cf301 i2c: Rename SPL/TPL_I2C_SUPPORT to I2C 
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
 2021-07-28 14:29:37 -04:00
Zong Li
564d630e26 riscv: sifive: fu740: Support i2c in spl 
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in
i2c node.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2021-07-06 20:24:25 +08:00
Zong Li
e2172aa83d riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller 
Enable the Opencores I2C controller on FU740

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2021-07-06 20:24:25 +08:00
Green Wan
c552debbd8 riscv: cpu: fu740: clear feature disable CSR 
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
 2021-05-31 16:35:55 +08:00
Green Wan
a74e9d899d riscv: cpu: fu740: Add support for cpu fu740 
Add SiFive fu740 cpu to support RISC-V arch

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 2021-05-31 16:35:53 +08:00