Commit graph

9 commits

Author SHA1 Message Date
Hai Pham
b092f96290 clk: renesas: Add R8A779A0 clock tables
Add clock tables for R8A779A0 V3U SoC from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
--
Marek: - Add .reset_modemr_offset
       - Sync tables from Linux 5.12
       - Rebase on latest u-boot
2021-06-24 20:22:17 +02:00
Marek Vasut
44c78aa7ac clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.

Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham <hai.pham.ud@renesas.com>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24 20:22:17 +02:00
Marek Vasut
e935409199 clk: renesas: Make reset controller modemr register offset configurable
The MODEMR register offset changed on R8A779A0, make the MODEMR offset
configurable. Fill the offset in on all clock drivers. No functional
change.

Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from
struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21 15:00:17 +02:00
Hai Pham
12dd238a64 clk: renesas: Add support for RPCD2 clock
This supports RPCD2 clock handling. While at it, add the check point
for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd
number

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21 15:00:17 +02:00
Marek Vasut
f7b4e4c094 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12
Synchronize R-Car Gen3 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21 15:00:16 +02:00
Adam Ford
e9a52c4439 clk: renesas: Add R8A774A1 clock tables
This sync's the clock tables with the official release from
Linux 5.8-RC2 and update r8a774a1_mstp_table from Ref Manual
v1.00.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25 11:16:39 +02:00
Marek Vasut
72242e5439 clk: renesas: Synchronize Gen3 tables with Linux 5.0
Synchronize R-Car Gen3 clock tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
716d775286 clk: renesas: Add PE clock handling
The PE clock have two parents, add support for picking the correct
one and deriving the clock from it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Marek Vasut
58f1788f47 clk: renesas: Pull Gen3 specific bits into separate header
Extract the macros specific to Gen3 clock into a separate header.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00