Commit graph

2986 commits

Author SHA1 Message Date
Michal Simek
2661081c30 ARM64: zynqmp: List secondary software boot modes
Using alternative bootmode field to support automatic secondary boot
modes. It is purely software setting where SW modes are using free
bootmode combinations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-12-02 14:35:57 +01:00
Lukasz Majewski
4db4d42ee2 imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)
This patch extends the imx6 clock code to enable or disable the EIM
slow clock, which in necessary when one wants to use EIM interface t
o read/write from external memory (e.g. NOR).

Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
2016-11-30 09:57:19 +01:00
Eric Nelson
a425bf7281 ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines
The DDR calibration routines are gated by conditionals for the
i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.

Also, since only the Novena board currently uses the dynamic
DDR calibration routines, these routines waste space on other
boards using SPL.

Add a KConfig entry to allow boards to selectively include the
DDR calibration routines.

Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29 16:40:37 +01:00
Eric Nelson
48c7d4379b mx6: ddr: add routine to return DDR calibration data
Add routine mmdc_read_calibration() to return the output of DDR
calibration. This can be used for debugging or to aid in construction
of static memory configuration.

This routine will be used in a subsequent patch set adding a virtual
"mx6memcal" board, but could also be useful when gathering statistics
during an initial production run.

Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29 16:40:25 +01:00
Eric Nelson
7f17fb7400 mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
The DDR calibration routines have scattered support for bus
widths other than 64-bits:

-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.

Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.

This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2016-11-29 16:40:12 +01:00
Eric Nelson
c8c3515508 imx: mx6: ddr: add register MPZQLP2CTL for LPDDR2
Add constants for the MPZQLP2CTL DDR register for both
banks to allow setting the LPDDR2 timing values in
.cfg files using a named constant instead of hex addresses
as is currently done in mx6slevk and other board files.

Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29 16:38:10 +01:00
Max Krummenacher
15fde0fc11 imx: make ipu's di configurable
The ipu has two display interfaces. Make the used one a parameter
in struct display_info_t instead of using unconditionally DI0.
DI0 is the default setting.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2016-11-29 16:33:21 +01:00
Stefano Babic
2d221489df Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
2016-11-29 16:28:28 +01:00
Tom Rini
ed77ccd014 Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	arch/arm/Kconfig
2016-11-25 17:39:54 -05:00
Alison Wang
3db86f4bbd armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled
As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22 11:40:24 -08:00
Alison Wang
e2c18e40b1 armv8: fsl-layerscape: SMP support for loading 32-bit OS
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22 11:40:24 -08:00
Alison Wang
ec6617c397 armv8: Support loading 32-bit OS in AArch32 execution state
To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.

The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.

Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22 11:40:24 -08:00
Priyanka Jain
9ae836cde7 armv8: fsl-layerscape: Add NXP LS2088A SoC support
The QorIQ LS2088A SoC is built on layerscape architecture.

It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22 11:37:54 -08:00
Priyanka Jain
f6b96ff665 armv8: lsch3: Use SVR based timer base address detection
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.

Use SVR based timer base address detection to avoid compile time #ifdef.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22 11:37:31 -08:00
Priyanka Jain
f6a70b3a92 armv8: lsch3: Add generic get_svr() in assembly
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22 11:37:07 -08:00
Tom Rini
081abb1309 Merge branch 'master' of git://git.denx.de/u-boot-spi 2016-11-22 07:57:23 -05:00
Tom Rini
187f9dc3f7 TI: Remove CONFIG_OMAP_COMMON in favor of CONFIG_ARCH_OMAP2
With the move to arch/arm/mach-omap2 there are now very few uses of
CONFIG_OMAP_COMMON and further they can all be replaced with
CONFIG_ARCH_OMAP2, so do so.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-21 14:07:29 -05:00
Lokesh Vutla
140d76a9ee board: ti: amx3xx: Remove multiple EEPROM reads
Detect the board very early and avoid reading eeprom multiple times.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-21 13:59:25 -05:00
Lokesh Vutla
b64a7cb92d ARM: AMx3xx: Centralize early clock initialization
This is similar to Commit 93e6253d11 ("ARM: OMAP4/5: Centralize
early clock initialization") that was done for OMAP4+, reflecting the same
for AM33xx and AM43xx SoCs to centralize clock initialization.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add setup_early_clocks that calls setup_clocks_for_console for
        ti81xx]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-21 13:58:55 -05:00
Chris Packham
ebfa18cb3d spi: kirkwood_spi: implement mvebu_spi_set_mode()
Set the appropriate bits in the interface config register based
on the SPI_ mode flags.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2016-11-18 13:04:52 +05:30
Tom Rini
9e40ea04e9 Patch queue for efi - 2016-11-17
Highlights this time around:
 
   - x86 efi_loader support
   - hello world efi test case
   - network device name is now representative
   - terminal output reports modes correctly
   - fix psci reset for ls1043/ls1046
   - fix efi_add_runtime_mmio definition for x86
   - efi_loader support for ls2080
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2016-11-17

Highlights this time around:

  - x86 efi_loader support
  - hello world efi test case
  - network device name is now representative
  - terminal output reports modes correctly
  - fix psci reset for ls1043/ls1046
  - fix efi_add_runtime_mmio definition for x86
  - efi_loader support for ls2080
2016-11-17 11:46:45 -05:00
Alexander Graf
b7b8410a8f ls2080: Exit dpaa only right before exiting U-Boot
On ls2080 we have a separate network fabric component which we need to
shut down before we enter Linux (or any other OS). Along with that also
comes configuration of the fabric using a description file.

Today we always stop and configure the fabric in the boot script and
(again) exit it on device tree generation. This works ok for the normal
booti case, but with bootefi the payload we're running may still want to
access the network.

So let's add a new fsl_mc command that defers configuration and stopping
the hardware to when we actually exit U-Boot, so that we can still use
the fabric from an EFI payload.

For existing boot scripts, nothing should change with this patch.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
[agraf: Fix x86 build]
2016-11-17 14:18:55 +01:00
Peng Fan
97c16dc8bf imx: mx6ull: update the REFTOP_VBGADJ setting
According to design team, we need to set REFTOP_VBGADJ
in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
actually table is as below:

  '000" - set REFTOP_VBGADJ[2:0] to 3'b000
  '001" - set REFTOP_VBGADJ[2:0] to 3'b001
  '010" - set REFTOP_VBGADJ[2:0] to 3'b010
  '011" - set REFTOP_VBGADJ[2:0] to 3'b011
  '100" - set REFTOP_VBGADJ[2:0] to 3'b100
  '101" - set REFTOP_VBGADJ[2:0] to 3'b101
  '110" - set REFTOP_VBGADJ[2:0] to 3'b110
  '111" - set REFTOP_VBGADJ[2:0] to 3'b111

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
2016-11-16 20:53:55 +01:00
Siva Durga Prasad Paladugu
e1992276c3 ARM64: zynqmp: Add support for SD1 with level shifters bootmode
Add support for SD1 with level shifters bootmode.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:28:05 +01:00
Keerthy
06d43c808d arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode
While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-13 15:54:36 -05:00
Stephen Warren
1ab557a074 armv8: add hooks for all cache-wide operations
SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-11-07 14:36:29 -08:00
Kever Yang
7d6c78f573 rk3288: sdram: auto-detect the capacity
Add support for rk3288 dram capacity auto detect, support DDR3 and
LPDDR3, DDR2 is not supported.
The program will automatically detect:
- channel number
- rank number
- column address number
- row address number

The dts file do not need to describe those info after apply this patch.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
2016-10-30 13:29:06 -06:00
Simon Glass
5564ed5dd9 rockchip: rk3288: Move rockchip_get_cru() out of the driver
This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-30 13:29:06 -06:00
Simon Glass
c8a6bc9683 rockchip: rk3399: Move rockchip_get_cru() out of the driver
This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-30 13:29:06 -06:00
Simon Glass
92ac73e4c2 rockchip: rk3036: Move rockchip_get_cru() out of the driver
This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-30 13:29:06 -06:00
Chen-Yu Tsai
31633a5677 sunxi: Add support for SID e-fuses on sun9i
The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses
are at an offset of 0x200 within the SID address space.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30 11:38:04 +01:00
Philipp Tomsich
7962a8d5a4 sunxi: add initial clock setup for sun9i for SPL
This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).

[wens@csie.org: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30 11:38:04 +01:00
Philipp Tomsich
ea1af9f26b sunxi: add gtbus-initialisation for sun9i
On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).

Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.

[wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30 11:38:04 +01:00
Philipp Tomsich
297bb9e0fc sunxi: DRAM initialisation for sun9i
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.

With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.

[wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks]
[hdegoede@redhat.com: Fix checkpatch warnings]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30 11:38:04 +01:00
Amit Singh Tomar
9d6c9d988f sunxi: A64: enable USB support
Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare minimum DT bits to the A64 .dtsi and enable the controllers
and the PHY on the Pine64.
This is limited to the first USB controller at the moment, which is
connected to the lower USB socket on the Pine64 board.
[Andre: remove unneeded defines, enable OHCI, add commit message]

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30 11:38:04 +01:00
Tom Rini
4f892924d2 Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	common/Kconfig
	configs/dms-ba16_defconfig
2016-10-28 11:12:03 -04:00
Jagan Teki
f4b7532f82 arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support
Boot Log for i.CoreM6 DualLite/Solo Starter Kit:
-----------------------------------------------

U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6SOLO rev1.3 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 31C
Reset cause: POR
DRAM:  256 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
** Unable to read file boot.scr **
reading zImage
6741808 bytes read in 341 ms (18.9 MiB/s)
Booting from mmc ...
reading imx6dl-icore.dtb
30600 bytes read in 19 ms (1.5 MiB/s)
   Booting using the fdt blob at 0x18000000
   Using Device Tree in place at 18000000, end 1800a787

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0

Boot Log for i.CoreM6 Quad/Dual Starter Kit:
--------------------------------------------

U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6Q rev1.2 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 28C
Reset cause: POR
DRAM:  512 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
icorem6qdl>

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26 16:53:16 +02:00
Peng Fan
ac1475ae29 imx: mx7: Add plugin support
Add mx7_plugin.S which calls boot rom setup function, generate the second ivt,
and jump back to boot rom.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-24 10:57:16 +02:00
Peng Fan
a45eb2674d imx: mx6: Add plugin support
Add mx6_plugin.S which calls boot rom setup function, generate the second ivt,
and jump back to boot rom.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
2016-10-24 10:57:16 +02:00
Alexander Graf
3ee655ed83 arm: Add PSCI shutdown function
Using PSCI you can not only reset the system, you can also shut it down!
This patch exposes a function to do exactly that to whatever code wants
to make use of it.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-18 09:08:08 +02:00
Alexander Graf
51bfb5b6f5 arm: Disable HVC PSCI calls by default
All systems that are running on armv8 are running bare metal with firmware
that implements PSCI running in EL3. That means we don't really need to expose
the hypercall variants of them.

This patch leaves the code in, but makes the code explicit enough to have the
compiler optimize it out. With this we don't need to worry about hvc vs smc
calling convention when calling psci helper functions.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-18 09:08:08 +02:00
Tom Rini
711b534120 Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/ls1021aqds.h
	include/configs/ls1021atwr.h
2016-10-12 08:29:42 -04:00
Tom Rini
f5fd45ff64 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-10-08 09:33:37 -04:00
Lokesh Vutla
1f95770807 ARM: AM437X: Add Silicon ID support
Add silicon ID code for AM437x silicon. This can be used to print
the cpu info using CONFIG_DISPLAY_CPUINFO.
Also printing "CPU :" along with cpu name in order to be consistent
with other OMAP platforms.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-10-08 09:33:36 -04:00
Alexander Graf
692fcdd800 arm: Add return value argument to longjmp
The normal longjmp command allows for a caller to pass the return value
of the setjmp() invocation. This patch adds that semantic to the arm
implementation of it and adjusts the efi_loader call respectively.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-08 09:33:34 -04:00
Masahiro Yamada
43ebbfc39f ARM: keystone: rename clk_get_rate() to ks_clk_get_rate()
The KeyStone platform has its own clk_get_rate() but its prototype
is different from that of the common-clk (clk-uclass) framework.

Prefix the KeyStone specific implementation with ks_ in order to
avoid name-space conflict.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-08 09:33:13 -04:00
tomas.melin@vaisala.com
f61c9bcdfd ARM: Add register defines for am33xx ePWM registers
Register definitions needed for configuring the
ePWM module.

Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
2016-10-06 21:00:53 -04:00
Keerthy
d31d4a2d75 ARM: Introduce function to switch to hypervisor mode
On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.

Cc: beagleboard-x15@googlegroups.com
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06 20:58:16 -04:00
Adam Oleksy
59a51a1055 ARM64: Add support for some of atomic64 operations
These functions are needed in UBI/UBIFS on ZynqMP platform (ARM64).

Signed-off-by: Adam Oleksy <adam.oleksy@nokia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2016-10-06 20:57:42 -04:00
Robert P. J. Day
fc0b5948e0 Various, accumulated typos collected from around the tree.
Fix various misspellings of:

 * deprecated
 * partition
 * preceding,preceded
 * preparation
 * its versus it's
 * export
 * existing
 * scenario
 * redundant
 * remaining
 * value
 * architecture

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2016-10-06 20:57:40 -04:00