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53 commits

Author SHA1 Message Date
Aaron Williams
91e34fcb41 mips: octeon Add cvmx/cvmx-lmcx-defs.h header 
This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
 2020-10-07 20:25:57 +02:00
Aaron Williams
75168b4aa7 mips: octeon: Add octeon-model.h header 
This header is used by the upcoming DDR driver and potentially by other
drivers ported from the 2013 Cavium / Marvell U-Boot repository.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
 2020-10-07 20:25:57 +02:00
Aaron Williams
0dc4ab9c43 mips: octeon: Initial minimal support for the Marvell Octeon SoC 
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.

Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
 2020-07-18 15:47:50 +02:00