There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.
Move these options to Kconfig and tidy up board configuration:
CONFIG_FIT
CONFIG_OF_BOARD_SETUP
CONFIG_OF_SYSTEM_SETUP
CONFIG_FIT_SIGNATURE
CONFIG_FIT_BEST_MATCH
CONFIG_FIT_VERBOSE
CONFIG_OF_STDOUT_VIA_ALIAS
CONFIG_RSA
Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.
Note: Masahiro's moveconfig.py script is amazing.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
Various boards have the wrong Kconfig ordering now. To avoid a misleading
diff in the next patch, reorder the configuration correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
The option was renamed to CONFIG_CONSOLE_ROTATION and Rockchip boards
were not updated. However this option is is not needed by default for
Rockchip since we don't need a rotated console for current boards. So just
remove the old option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enabling CONFIG_DISPLAY breaks building for some architectures
(microblaze-generic), so we disable CONFIG_DISPLAY in Kconfig
by default and enable this option in defconfigs. CONFIG_DISPLAY
depends on CONFIG_I2C_EDID, so add and enable it in defconfigs, too.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
At present we use the same peripheral ID for clocks and pinctrl. While this
works it is probably better to use the device tree clock binding ID for
clocks. We can use the clk_get_by_index() function to find this.
Update the clock drivers and the code that uses them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Switch to using tiny-printf for the firefly SPL, this reduces the SPL by
around 1800 bytes bringing it back under the 32k limit for both gcc 4.9
and gcc 5.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Now that u-boot relocates the malloc area in SPL to SDRAM, with the
malloc area sitting below the SPL_STACK_R_ADDR the
SPL_STACK_R_MALLOC_SIMPLE_LEN needs to be set explicitly for
rockchip as its SPL_STACK_R_ADDR (512kb) is smaller then
STACK_R_MALLOC_SIMPLE_LEN (1Mb).
Using the same value as SYS_MALLOC_F_LEN (8kb) is enough to load u-boot
from SD card.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can
remove from SPL stage.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are already Kconfig options for SPI drivers, but we
have not moved them from config.h to defconfig files. This
commit does this in a batch.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
No UART driver was specified in defconfig, thus
DEBUG_UART_ALTERA_JTAGUART was incorrectly selected by default since
commit 220e8021af added a new Altera UART
driver.
Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>
With LED support enabled the SPL easily goes over the size limit (e.g.
with both Debians gcc 4.9 and 5.2 cross-compilers). Turn off LED support
in the SPL to reduce the size just enough for those compilers.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tweaked commit subject to remove _SUPPORT
Signed-off-by: Simon Glass <sjg@chromium.org>
The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.
This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.
Signed-off-by: Simon Glass <sjg@chromium.org>
