Commit graph

10 commits

Author SHA1 Message Date
Tom Rini
8991fed97d mips: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-24 16:34:45 -04:00
Tom Rini
aa6e94deab global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Lars Povlsen
7048bb13b2 mips: vcoreiii: Fix cache coherency issues
This patch fixes an stability issue seen on some vcoreiii targets,
which was root caused to a cache inconsistency situation.

The inconsistency was caused by having kuseg pointing to NOR area but
used as a stack/gd/heap area during initialization, while only
relatively late remapping the RAM area into kuseg position.

The fix is to initialize the DDR right after the TLB setup, and then
remapping it into position before gd/stack/heap usage.

Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2020-04-09 18:55:59 +02:00
Horatiu Vultur
72e224b864 mips: mscc: serval: Fix reset
In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-05-03 16:42:23 +02:00
Horatiu Vultur
1895b87e84 MSCC: Add support for Serval SoC family.
As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:28:09 +01:00
Horatiu Vultur
055125171a MSCC: Add support for Servalt SoC family.
As Ocelot, Luton and Jaguar2, this family of SoCs are found
in Microsemi Switches solution.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23 18:27:26 +01:00
Horatiu Vultur
e7a0de2c31 MSCC: Add support for Jaguar2 SOC family
As the Ocelot and Luton SoCs, this family of SoCs are found
in Microsemi Switches solution.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Gregory CLEMENT
6bd8231a6d MSCC: add support for Luton SoCs
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19 15:23:01 +01:00
Gregory CLEMENT
dd1033e4e0 MSCC: add support for Ocelot SoCs
This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19 15:23:01 +01:00