So far we stated the lack of a lowlevel() init function for the
Allwinner F1C100s board by defining the respective SKIP_* symbol in the
board's defconfig. However we don't expect any *board* to employ such
low level code, so expect this to be never used for the ARMv5 Allwinner
SoCs.
Select the appropriate symbols in the Kconfig, so that we can remove
them from the defconfig, and avoid putting them in future defconfigs for
other boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Traditionally we assumed that every Allwinner board would come with at
least 256 MB of DRAM, and set our DRAM layout accordingly. This affected
both the default load addresses, but also U-Boot's own address
expectations (like being loaded at 160 MB).
Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So
far we special-cased those *chips*, as there was only one chip per DRAM
size. However new chips force us to take a more general approach.
Introduce a Kconfig symbol, which provides the minimum DRAM size of the
board. If nothing else is specified, we use 256 MB, and default to
smaller values for those co-packaged SoCs.
Then select the different DRAM maps according to this new symbol, so
that different SoCs with the same DRAM size can share those definitions.
Inspired by an idea from Icenowy.
This is just refactoring: compiled for all boards before and after this
patch: the binaries were identical.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The enable_caches function in architecture-specific board code is only
necessary for V7A CPUs, code for both V8A and ARM926 have already
declared this function.
Only provide our implementation of enable_caches() for V7A CPUs.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The H616 SoC uses the same SPI IP as the H6, also shares the same clocks
and reset bits.
The only real difference is a slight change in the pin assignment: the
H6 uses PC5, the H616 PC4 instead. This makes for a small change in
our spi0_pinmux_setup() routine.
Apart from that, just extend the H6 #ifdef guards to also cover the H616,
using the shared CONFIG_SUN50I_GEN_H6 symbol.
Also use this symbol for the Kconfig dependency.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Ivan Shishkin <s45rus@gmail.com>
This is not needed and we should avoid typedefs. Use the struct instead
and rename it to indicate that it really is a legacy struct.
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.
So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.
Fixes: 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This option is used only by the phy-sun4i-usb driver, which does not
inherently depend on the ARM architecture.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
KConfig has range option, use it instead of notice in the option
descrition.
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
We want to keep all of the default values for SPL_LDSCRIPT in the same
place both for overall clarity as well as not polluting unrelated config
files.
Signed-off-by: Tom Rini <trini@konsulko.com>
ARCH_SUNXI selects DM_SERIAL, so the condition can never be satisfied.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When CONFIG_UART0_PORT_F is defined, we try to configure two PortF pins
(usually used for the SD card) as UART0. Some SoCs use the mux value of
3 for this, while others use 4.
The combination of Kconfig symbols we currently use was not quite right:
we mis-configure the A31, A64, H6 and H616.
Going through the list in the pinctrl driver, there are only a few older
SoCs that use a value of 4, so revert the #ifdef clause, and name those
explicitly, instead of the other way around.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16
SoCs and all existing boards from the Linux v5.18-rc1 tag.
These changes are combined into one commit due to interdependencies:
- The unit addresses were removed from bitbanged I2C buses, which
drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts
and sun6i-a31-colombus.dts.
- The pinctrl nodes were renamed, including some used by the shared
header sunxi-reference-design-tablet.dtsi.
To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts
to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree.
This commit also adds the following new board devicetrees:
- sun5i-a13-licheepi-one.dts
- sun5i-a13-pocketbook-touch-lux-3.dts
- sun5i-gr8-evb.dts
- sun8i-a23-ippo-q8h-v1.2.dts
- sun8i-a23-ippo-q8h-v5.dts
- sun8i-a33-et-q8-v1.6.dts
- sun8i-a33-ippo-q8h-v1.2.dts
- sun8i-r16-nintendo-super-nes-classic.dts
As with the other SoCs, updates of note are conversion of GPIO pull-up
from pinconf to GPIO flags and renaming the detection GPIO properties in
the USB PHY nodes.
Signed-off-by: Samuel Holland <samuel@sholland.org>
When the Allwinner BROM loads the SPL from an eMMC boot partition, it
sets the boot source byte to the same value as when booting from the
user data partition. This prevents us from determining the boot source
to load U-Boot proper from the proper partition for sure.
The generic SPL MMC code already looks at the enabled boot partition
number, to load U-Boot proper from the same partition, but this fails
if there is nothing bootable in this partition, as the BROM then
silently falls back to the user data partition, which the SPL misses.
To learn about the actual boot source anyway, we repeat the algorithm
the BROM used to select the boot partition in the first place:
- Test EXT_CSD[179] to check if an eMMC boot partition is enabled.
- Test EXT_CSD[177] to check for valid MMC interface settings.
- Check if BOOT_ACK is enabled.
- Check the beginning of the first sector for a valid eGON signature.
- Load the whole SPL.
- Recalculate the checksum to verify the SPL is valid.
If one of those steps fails, we bail out and continue loading from the
user data partition. Otherwise we load from the selected boot partition.
Since the boot source is needed twice in the boot process, we cache the
result of this test to avoid doing this costly test multiple times.
This allows the very same image file to be put onto an SD card, into the
eMMC user data partition or into the eMMC boot partition, and safely
loads the whole of U-Boot from there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
BSP boot0 executes resistor calibration before clocks are initialized.
Let's do that.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fix non working console on uart2, that seems releated to both
Allwinner H2+ and H3.
Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com>
[Andre: remove H2+, rearrange pin setup order]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Commit 5bc4cd05d7 ("sunxi: move non-essential code out of s_init()")
moved the call to eth_init_board() from s_init() into board_init_f().
This means it's now only called from the SPL, which makes sense for
most of the other moved low-level functions. However the GMAC pinmux and
clock setup in eth_init_board() was not happy about that, so it broke
the sun7i GMAC.
Since Ethernet is of no use in the SPL anyway, just move the call into
board_init(), which is only run in U-Boot proper.
This fixes Ethernet operation for the A20 SoCs, which broke in
v2022.04-rc1, with the above mentioned commit.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Petr Štetiar <ynezz@true.cz> [a20-olinuxino-lime2]
Commit 7945caf22c ("arm: sunxi: Enable SPI/SPI-FLASH support for A64")
selected CONFIG_SPI by default on all Allwinner A64 boards, even though
only 4 out of the 14 A64 boards have a SPI flash chip. All other SoCs
had to manually select DM_SPI and friends, even though they are a
platform property (the sunxi SPI driver is DM_SPI only).
Clean this up to allow easy selection of SPI flash support in U-Boot
proper, by selecting DM_SPI and DM_SPI_FLASH *if* CONFIG_SPI is
selected, for *all* Allwinner SoCs. This simplifies the defconfig for
two Libretech boards already.
Also remove the forced CONFIG_SPI from the A64 Kconfig, instead let the
four boards which allow SPI booting select this explicitly.
Any board wishing to support SPI flash in U-Boot proper now just defines
CONFIG_SPI and CONFIG_SPI_FLASH_<vendor> in its defconfig, Kconfig takes
care of the rest.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Enable SPI boot in SPL on SUNIV architecture and use
it in the licheepi nano that uses the F1C100s.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The SUNIV SoCs come with a sun6i-style SPI controller at the base address
of sun4i SPI controller. The module clock of the SPI controller is
missing which leaves us running directly from the AHB clock, which is
set to 200MHz.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[Icenowy: Original implementation]
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Jesse: adaptation to Upstream U-Boot]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
In contrast to other Allwinner SoCs the F1C100s BROM does not store a
boot source indicator in the eGON header in SRAM. This leaves the SPL
guessing where we were exactly booted from, and for instance trying
the SD card first, even though we booted from SPI flash.
By inspecting the BROM code and by experimentation, Samuel found that the
top of the BROM stack contains unique pointers for each of the boot
sources, which we can use as a boot source indicator.
This patch removes the existing board_boot_order bodge and replace it
with a proper boot source indication function.
The only caveat is that this only works in the SPL, as the SPL header
gets overwritten with the exception vectors, once U-Boot proper takes
over. Always return MMC0 as the boot source, when called from U-Boot
proper, as a placeholder for now, until we find another way.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Suggested-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add support for F1C100s internal dram controller.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Both armv7 and arm926ejs use this timer code so move it to mach-sunxi.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When we added Allwinner SoC support to ARMv8, we needed to pull in an
implementation of lowlevel_init() calling the C function s_init(), as
sunxi required it as this time.
The last few patches got rid of this bogus requirement, and as sunxi was
still the only user, we can now remove this lowlevel_init.S from ARMv8
altogether.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied
from the original BSP U-Boot. The comment speaks of this being required
before DRAM access gets enabled, but there is no indication that this
would actually be required that early.
Move this out of s_init(), into board_init_f(). Since this actually only
affects a very few older SoCs, the actual code goes into the cpu/armv7
directory, to move it out of the way for all other SoCs.
This also uses the opportunity to convert some #ifdefs over to the fancy
IS_ENABLED() macros used in actual C code.
We keep the s_init() stub around for now, since armv8's lowlevel_init
still relies on it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
maintenance operations are done. As we do those things still in start.S,
we need to move the SMPEN bit setting there, too.
This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR
very early in start.S, and moves sunxi boards over to use that instead
of the custom code we had in our board.c file (where it was called
technically too late).
In practice we got away with this so far, because at this point all the
other cores were still in reset, so any broadcasting would have been
ignored anyway. But it is architecturally cleaner to do it early, and
we move a core specific piece of code out of board.c.
This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few
years back, and moves the respective logic into the new Kconfig entry.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
So far all Allwinner based boards were doing some not-so-lowlevel-setup
in lowlevel's s_init() routine.
This includes the initial clock, timer and pinmux setup, among other
things. This is clearly out of the "absolute bare minimum to get started"
scope that lowlevel_init.S suggests for this function.
Since we have an SPL, which is called right after s_init(), move those
calls to our board_init_f() function. As we overwrite this only for
the SPL, this has the added benefit of not doing this setup *again*
shortly afterwards, when running U-Boot proper.
This makes gpio_init() to be called from the SPL only, so pull this code
into a CONFIG_SPL_BUILD protected part to avoid build warnings.
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that
it has to be set before read calibration and cleared afterwards. This is
already done for first rank, but not for second (copy & paste error.)
Fix it.
Fixes: f4317dbd06 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Kconfig symbol is missing CONFIG_ prefix, so compiler will always
skip ODT configuration.
Fix symbol name.
Fixes: f4317dbd06 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
For sunxi boards with the AXP209, AXP221, AXP809, and AXP818 PMICs
(plus possibly others, I only confirmed the datasheets for these),
it is sometimes desirable to not boot whenever the device is
plugged in. An example would be when using the NTC CHIP inside a
PocketCHIP.
This provides a configurable option to check if bit 0 of
register 0 of the PMIC says it was powered because of a power button
press (0) or a plug-in event (1). If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
[Andre: reword to speak of boot, remove #ifdefs]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The calls for flipping bits in the Allwinner pin controller registers
were using unnecessarily complex pointer arithmetic.
Improve readability by simplifying the expression.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The GPIO and pinctrl drivers need these setters for pin configuration.
Since they are DM drivers, they should not be using hardcoded base
addresses. Factor out variants of the setter functions which take a
pointer to the GPIO bank's MMIO registers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The return values of these functions are always zero, and they are
never checked. Since they are not needed, remove them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add parameter spl_boot_device to spl_parse_board_header(), which allows
the implementations to see from which device we are booting and do
boot-device-specific checks of the image header.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the sunxi board code. Fix the build with
SYSRESET enabled by omitting the function from the board code in that
case. The code still needs to be kept around for use in SPL.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Stefan Roese <sr@denx.de>
The more recent Allwinner SoCs BootROMs can actually load SPL images
larger than 32KB. We use this on the H616 to fit the extra code needed
for the PMIC into the image, and have provisions in board.c to respect
that larger SPL size when booting from MMC.
However the sunxi SPL SPI loader has a hardcoded load offset of 32KB,
which will fail on the H616.
To fix this, use the same algorithm we use for MMC: if the SPL size is
smaller than 32KB, we use 32KB, otherwise we expect the U-Boot payload
directly after the SPL code.
This prepares for SPI booting with larger SPLs like on the H616.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Now that the last users of legacy I2C (outside of SPL) have been
resolved, we can enable DM_I2C at the sunxi architecture level.
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Two displays supported by the sunxi display driver (each one used by a
single board) require initialization over I2C. Both previously used
i2c_soft; replace this with the i2c-gpio instance that already exists in
those boards' device trees (sun5i-a13-utoo-p66 and sun6i-a31-colombus).
Since the i2c-gpio nodes are not referenced by any other node in the
device trees (the device trees have no panel node), the I2C bus is
selected by its node name.
This panel initialization code was the only i2c_soft user, so the
i2c_soft GPIO setup code can be removed now as well.
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The pmic_bus functions are used in both SPL (for regulator setup) and
U-Boot proper (for regulator setup, SID access, GPIO, and poweroff).
Currently, pmic_bus conflicts with DM_I2C because it uses the legacy I2C
interface. This commit makes pmic_bus dual-compatible with either the
legacy I2C functions or the newly-added PMIC_AXP driver (which uses
DM_I2C). In turn, this allows platforms to start transitioning to DM_I2C
in U-Boot proper, without breaking boards that still depend on the
legacy I2C interface for other reasons.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Instead of using the SoC symbols to decide the bus type, use whichever
bus driver is actually enabled. This allows collapsing all of the AXP2xx
and AXP8xx variants into one "else" case. It also has the advantage of
falling back to I2C when the other bus drivers are disabled; this works
because all of the PMICs support I2C in addition to other interfaces.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This bus controller is used to communicate with an X-Powers AXP PMIC.
Currently, various drivers access PMIC registers through a platform-
specific non-DM "pmic_bus" interface, which depends on the legacy I2C
framework. In order to convert those drivers to use DM_PMIC, this bus
needs a DM_I2C driver.
Refactor the rsb functions to take the base address as a parameter,
and implement both the existing interface (which is still needed in
SPL) and the DM_I2C interface on top of them.
The register for switching between I2C/P2WI/RSB mode is the same across
all PMIC variants, so move that to the common header.
There are only a couple of pairs of hardware/runtime addresses used
across all PMIC variants. So far the code expected only the "primary"
pair, but some PMICs like the AXP305 and AXP805 use the secondary pair,
so add support for that to the DM driver as well.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This bus controller is used to communicate with an X-Powers AXP PMIC.
Currently, various drivers access PMIC registers through a platform-
specific non-DM "pmic_bus" interface, which depends on the legacy I2C
framework. In order to convert those drivers to use DM_PMIC, this bus
needs a DM_I2C driver.
Refactor the p2wi functions to take the base address as a parameter,
and implement both the existing interface (which is still needed in
SPL) and the DM_I2C interface on top of them.
The register for switching between I2C/P2WI/RSB mode is the same across
all PMIC variants. Move that to the common header, so it can be used by
both interface implementations.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
AXP_PMIC_BUS enables communication with a specific AXP PMIC at a
PMIC-dependent I2C/P2WI/RSB bus address. It is automatically selected
as a dependency of the PMIC driver. It should not be selectable by the
user when no PMIC is chosen.
AXP_GPIO uses the pmic_bus functions, and also depends on a specific
PMIC header to pick up register definitions.
Both of these changes have no impact on any existing configs, since
the code does not compile if the dependencies are not met.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
SUN8I_RSB should not be selected by MACH_SUN8I, because the hardware
is not present in half of those SoCs (H3/H5, R40, and V3s). Move the
selection to the SoCs where the hardware actually exists.
As it currently stands, selecting that option also requires using it in
some way, which is not the case for one A80 board. Since we have only
three A80 boards in total, we select it their via their defconfigs.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: fixing up Sunchip_CX-A99 build]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
