Commit graph

77566 commits

Author SHA1 Message Date
Pali Rohár
6eb20bbff3 tools: kwbimage: Mark all local functions as static
Mark all local functions as static.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:15 +01:00
Marek Behún
3fc92a215b ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision
This is a cleaned up and fixed version of a patch
  mv_ddr: a380: fix SPLIT_OUT_MIX state decision

  in each pattern cycle the bus state can be changed
  in order to avoide it, need to back to the same bus state on each
  pattern cycle
by
  Moti Boskula <motib@marvell.com>

The original patch is not in Marvell's mv-ddr-marvell repository. It was
gives to us by Marvell to fix an issues with DDR training on some
boards, but it cannot be applied as is to mv-ddr-marvell, because it is
a very dirty draft patch that would certainly break other things, mainly
DDR4 training code in mv-ddr-marvell, since it changes common functions.

I have cleaned up the patch and removed stuff that seemed unnecessary
(when removed, it still fixed things). Note that I don't understand
completely what the code does exactly, since I haven't studied the DDR
training code extensively (and I suspect that no one besides some few
people in Marvell understand the code completely).

Anyway after the cleanup the patch still fixes isssues with DDR training
on the failing boards.

There was also a problem with the original patch on some of the Allied
Telesis' x530 boards, reported by Chris Packham. I have asked Chris to
send me some logs, and managed to fix it:
- if you look at the change, you'll notice that it introduces
  subtraction of cur_start_win[] and cur_end_win[] members, depending on
  a bit set in the current_byte_status variable
- the original patch subtracted cur_start_win[] if either
  BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
  subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
  was set
- from Chris Packham logs I discovered that the x530 board where the
  original patch introduced DDR training failure, only the
  BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
  patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
  current_byte_status variable
- this led me to the hypothesis that both cur_start_win[] and
  cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
  set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all
- this hypothesis also gains credibility when considering the commit
  title ("fix SPLIT_OUT_MIX state decision")

Hopefully this will fix things without breaking anything else.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
2022-01-14 11:39:15 +01:00
Marek Behún
28c1922675 board: gdsys: Drop Dirk Eibach from MAINTAINERS
I got an

<dirk.eibach@gdsys.cc>: host mxlb.ispgateway.de[80.67.18.126] said:
  554 Sorry, no mailbox here by that name. (in reply to RCPT TO command)

when sending e-mail to dirk.eibach@gdsys.cc.

Drop Dirk Eibach from MAINTAINERS of board/gdsys/a38x and
board/gdsys/mpc8308. The latter would be left maintainerless, add
Mario Six <mario.six@gdsys.cc> (he is also maintainer of the former
board).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 07:47:57 +01:00
Marek Behún
eadc4f512f ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination
Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
mode"), Asynchornous Mode was only used when the CPU Subsystem Clock
Options[4:0] field in the SAR1 register was set to value 0x13: CPU at
2 GHz and DDR at 933 MHz.

Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
mode") added support for Asynchornous Modes with frequencies other than
933 MHz (but at least 467 MHz), but the code it added to check for
whether Asynchornous Mode should be used is wrong: it checks whether the
frequency setting in board DDR topology map is set to value other than
MV_DDR_FREQ_SAR.

Thus boards which define a specific value, greater than 400 MHz, for DDR
frequency in their board topology (e.g. Turris Omnia defines
MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that
commit.

The A38x Functional Specification, section 10.12 DRAM Clocking, says:
  In Synchornous mode, the DRAM and CPU clocks are edge aligned and run
  in 1:2 or 1:3 CPU to DRAM frequency ratios.

Change the check for whether Asynchornous Mode should be used according
to this explanation in Functional Specification.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 07:47:57 +01:00
Tony Dinh
1b24de6e9f arm: kirkwood: iConnect : Update board maintainer
Add myself as maintainer.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 07:47:57 +01:00
Tony Dinh
bbebd5b0a5 arm: kirkwood: iConnect : Add PCIe late init
- Add board_late_init function to enable pci_init

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 07:47:57 +01:00
Tony Dinh
531d4bb04e arm: kirkwood: iConnect : Add PCIe related configs
- Add MVEBU PCIe configs
- Also add SYS_THUMB_BUILD to keep u-boot image size within 512K

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 07:47:57 +01:00
Pierre Bourdon
c03f4da187 mtd: nand: pxa3xx: use marvell, prefix for custom DT properties
The DT properties for the "enable-arbiter" and "keep-config" config
knobs were previously named inconsistently:

- The u-boot driver used "nand-enable-arbiter" and "nand-keep-config"
  names, without Marvell prefixes.

- The Linux driver uses "marvell,nand-keep-config" ("enable-arbiter"
  does not exist anymore in recent kernels, but it also used to be
  "marvell,nand-enable-arbiter").

- The device trees almost all use "marvell," prefixed names, except for
  one single instance of "nand-enable-arbiter" without vendor prefix.

This commit standardizes on the vendor prefixed version, making the
u-boot driver read from DT props "marvell,nand-enable-arbiter" and
"marvell,nand-keep-config". The one device tree using the unprefixed
version is also changed to use the new naming.

This has the side effect of making the previously no-op "marvell,"
config knobs already present in some DTs actually do something. This was
likely the original intention of the DT authors, but note that this
commit was not tested on every single impacted board.

Signed-off-by: Pierre Bourdon <delroth@gmail.com>
2022-01-14 07:47:57 +01:00
Pali Rohár
94c30f9c8f arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c
As explained in commit 3bedbcc3aa ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.

Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.

Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.

Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.

This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
35e29e89a3 arm: mvebu: Implement simple mvebu-reset driver for enabling/disabling PCIe ports
Enabling and disabling PCIe ports is done via address space of system
controller. All 32-bit Armada SoCs use low 4 bits in SoC Control 1 Register
for enabling and disabling some or more PCIe ports. Correct mapping needs
to be set in particular DTS files.

DT API for mvebu-reset is prepared for implementing resets also for other
HW blocks, but currently only PCIe is implemented via index 0.

Currently this driver is not used as PCIe ports are automatically enabled
by SerDes code executed by U-Boot SPL. But this will change in followup
patches.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
e7ff4271ab pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe()
After function mvebu_pcie_probe() returns U-Boot DM expects that PCIe link
is already up. In followup patches link initialization will be moved from
SPL to proper and therefore explicitly link up delay is required.

Delay mvebu_pcie_probe() for 100ms to ensure that PCIe link is up after
function finish. In the case when no card is connected to the PCIe slot,
this will delay probe time by 100ms, which should not be problematic.

This change fixes detection and initialization of some QCA98xx cards on
the first serdes when configured in x1 mode. Default configuration of
the first serdes on A385 is x4 mode, so it looks as if some delay is
required when x4 is changed to x1 and card correctly links with A385.
Other PCIe serdes ports on A385 are x1-only, and so they don't have this
problem.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
afef9f4215 pci: pci_mvebu: Split initialization of PCIe ports into 3 phases
In first phase just parse DT properties and fill struct mvebu_pcie. In
second phase setup all PCIe links (without enabling them). And in the last
third phase enable all PCIe links and create UCLASS_PCI device for each
one.

Because parsing of DT is done before UCLASS_PCI is created, we cannot use
DM for this action anymore. So remove .of_to_plat callback and replace it
by ad-hoc function for parsing DT properties and filling struct mvebu_pcie.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
137db2af14 pci: pci_mvebu: Remove dependency on SOC_REGS_PHY_BASE macro
SoC specific macro SOC_REGS_PHY_BASE is used for two things:

* calculation of base PCIe port address
* filling PCIe register with address of internal registers

For calculating base PCIe port address use function
ofnode_translate_address() which translates DT "assigned-addresses" to
final PCIe port address.

And for calculating address of internal registers use untranslated and
translated DT "assigned-addresses".

Basically this change reads SOC_REGS_PHY_BASE address indirectly from DT.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
6f4988f90c pci: pci_mvebu: Inline mvebu_pcie_port_parse_dt() function
Function mvebu_pcie_port_parse_dt() is called only from
mvebu_pcie_of_to_plat() function. Both these function parse DT properties
required to setup mvebu pcie. So inline mvebu_pcie_port_parse_dt() function
into mvebu_pcie_of_to_plat() to have all code related to parsing DT
properties at one place.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
537b0142b0 pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping
Do not call pci_set_region() for resources which were not properly mapped.
This prevents U-Boot to access unmapped memory space.

Update MBUS_PCI_MEM_SIZE and MBUS_PCI_IO_SIZE macros to cover all PCIe MEM
and IO ranges. Previously these macros covered only address ranges for the
first PCIe port. Between MBUS_PCI_IO_BASE and MBUS_PCI_MEM_BASE there is
space for six 128 MB long address ranges. So set MBUS_PCI_MEM_SIZE to value
of 6*128 MB. Similarly set MBUS_PCI_IO_SIZE to 6*64 KB.

Function resource_size() returns zero when start address is 0 and end
address is -1. So set invalid resources to these values to indicate that
resource has no mapping.

Split global PCIe MEM and IO resources (defined by MBUS_PCI_*_* macros)
into PCIe ports in mvebu_pcie_bind() function which allocates per-port
based struct mvebu_pcie, instead of using global state variables
mvebu_pcie_membase and mvebu_pcie_iobase. This makes pci_mvebu.c driver
independent of global static variables (which store the state of
allocation) and allows to bind and unbind the driver more times.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
2022-01-14 07:47:57 +01:00
Pali Rohár
2ac06f3e66 board: gdsys: a38x: Enable PCIe link 2 in spl_board_init()
A385 controlcenterdc board does not use PCI DM properly and touches some
PCIe devices directly in its board code.

This controlcenterdc spl_board_init() function expects that PCIe link is
already initialized. Link itself is initialized in a38x serdes code but
this will change in future and link initialization will be postponed from
U-Boot SPL to proper U-Boot.

So explicitly enable PCIe link 2 in spl_board_init() function via
SoC Control Register 1 to not break this code by future changes. This board
has PCIe link 2 just x1, so no additional initialization (except enabling
PCIe port) is needed.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
8f9e0f4d20 arm: mvebu: Convert board_pex_config() to CONFIG_SPL_BOARD_INIT
The only user of board_pex_config() weak function is A385 controlcenterdc
board. It looks like that code in its board_pex_config() function needs to
be executed after PCIe link is up. Therefore put this code into
spl_board_init() function which is called after a38x serdes initialization,
and therefore it is after the serdes hws_pex_config() function finishes
(which is the state before this change).

With this change completely remove board_pex_config() function as it is not
used anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Tom Rini
25711b07ca bloblist prep for standard passage
switch order of pinctrl and power domain calls
 various minor fixes
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Merge tag 'dm-pull-13jan22' of https://source.denx.de/u-boot/custodians/u-boot-dm

bloblist prep for standard passage
switch order of pinctrl and power domain calls
various minor fixes
2022-01-13 14:33:02 -05:00
Simon Glass
6c9e3d1fc0 bloblist: Relicense to allow BSD-3-Clause
This implementation is intended to be copied to other projects and
modified, to as to foster a standard means of communcating runtime
information between firmware projects.

The GPL-2 license is too restrictive for some projects, e.g. those
intended as reference implementations rather than designed for
collaborative open-source development.

Update the license to make this easier to share.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
20a1493530 bloblist: doc: Bring in the API documentation
FIx up various minor errors and add the API documentation to the bloblist
docs, since it is quite useful to see it in the same place.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
e50a24a045 bloblist: Add functions to obtain base address and size
Add a few convenience functions to obtain useful information about the
bloblist.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
99047f5d7f bloblist: Refactor Kconfig to support alloc or fixed
At present we do support allocating the bloblist but the Kconfig is a bit
strange, since we still have to specify an address in that case. Partly
this is because it is a pain to have CONFIG options that disappears when
its dependency is enabled. It means that we must have #ifdefs in the code,
either in the C code or header file.

Make use of IF_ENABLED_INT() and its friend to solve that problem, so we
can separate out the location of bloblist into a choice. Put the address
and size into variables so we can log the result.

Add the options for SPL as well, so we can use CONFIG_IS_ENABLED().

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
5938d654de bloblist: Use 'phase' consistently for bloblists
We typically refer to the different U-Boot builds that a board runs
through as phases. This avoids confusion with the word 'stage' which is
used with bootstage, for example. Fix up some bloblist Kconfig help
which uses the wrong term.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
1d8bbd76f0 bloblist: Use LOG_CATEGORY to simply logging
Use the convenience functions to improve readability.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
f16ec77784 bloblist: Use explicit numbering for the tags
At present if someone adds a tag in the middle of the list it works well
enough within a U-Boot build. But if these tags are used in another
project, or with an older version of SPL, the numbers make become
inconsistent.

Use explicit tag numbers that never change, to resolve this problem.
Allocate areas for existing U-Boot tags and set up an area for use by
projects and vendors, as well as for private use. Keep tags above
0x10000 unallocated for now.

Update bloblist_tag_name() and the tests to work with this new setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
f9abc1cac1 bloblist: Drop unused tags
The EC event log tag is no-longer used. The vboot handoff is now handled
by the vboot context instead.

Drop these unused tags.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
7f3b79af54 bloblist: Rename the SPL tag
Add a U_BOOT prefix to this tag since it is specific to the U-Boot
project.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
ff3bd4983c bloblist: Put the magic number first
It seems best to put the magic number right at the start of the bloblist
header, so it is easier to check. This is how devicetree works.

Make this change now, before other projects make use of bloblist. Other
changes may be needed / discussed, but that is TBD.

Add a checker function as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
f350f67764 fdt: Drop SPL_BUILD macro
This old macro is not needed anymore since we can use IS_ENABLED() now.
Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Simon Glass
78aac05eb1 stddef: Avoid warning with clang with offsetof()
Some bright sparks have decided that a cast on a constant cannot be a
constant, so offsetof() produces this warning on clang-10:

include/intel_gnvs.h:113:1: error: static_assert expression is not an
	integral constant expression
check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/kernel.h:284:2: note: expanded from macro 'check_member'
        offsetof(struct structure, member) == (offset), \
        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/stddef.h:20:32: note: expanded from macro 'offsetof'
                                ^
include/intel_gnvs.h:113:1: note: cast that performs the conversions of
	a reinterpret_cast is ot allowed in a constant expression
include/linux/stddef.h:20:33: note: expanded from macro 'offsetof'

Fix it by using the compiler built-in version, if available. This syncs
the function to the same implementation as Linux v5.16 in this header
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Andre Przywara
5ecdd529ae genboardscfg: limit to 240 jobs
When genboardscfg.py is run on machines with 255 or more cores, the
process will consume more than 1024 file descriptors, which is a common
standard ulimit for user processes. As a consequence it will fail with a
lenghty Python trace, with the almost hidden message:
OSError: [Errno 24] Too many open files

It's somewhat questionable whether that level of parallelity is actually
useful for genboardscfg, so we limit the *default* number of jobs to the
safe number of 240, to avoid the problem.
If a user persists, she can still force a higher number via the -j
parameter - hopefully having raised the ulimit accordingly beforehand.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Heinrich Schuchardt
880dbc5f80 sandbox: compatibility of os_get_filesize()
U-Boot define loff_t as long long. But the header
/usr/include/linux/types.h may not define it.
This has lead to a build error on Alpine Linux.

So let's use long long instead of loff_t for
the size parameter of function os_get_filesize().

Reported-by: Milan P. Stanić <mps@arvanta.net>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Brian Norris
dca7926c2c patman: Support absolute and ~user-relative alias files
Python doesn't naturally support tilde (~) as a user-home marker in
paths, but git-config does. So we need to resolve it before continuing.

We also shouldn't blindly join the top-level tree with the aliasesfile
path, because it might be an absolute path.

This resolves warnings like the following:

  Warning: Cannot find alias file '/path/to/source/tree/~/.git-email'

Seen when git-config is like:

  $ git config sendemail.aliasesfile
  ~/.git-email

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
2022-01-13 09:13:41 -07:00
Michal Simek
d8ef446fec dm: core: Switch order of pinctrl and power domain calls
The commit 3ad3077848 ("dm: core: device: enable power domain in probe")
introduced enabling power domain when device is probed.
By checking this sequence in Linux kernel was found that power domain is
handled first followed by pinctrl setting.

This patch is switching this order to follow Linux kernel that power
domains are handled first follow by pinctrl setting.

The issue was found on Xilinx Kria SOM where firmware is blocking setting
up pin configuration/muxes without enabling power domain for the specific
IP first.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Tom Rini
743c562d0c Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Add Apple M1 watchdog timer (Mark)
2022-01-13 08:00:02 -05:00
Tom Rini
43304e49fe Merge branch '2022-01-13-assorted-spelling-fixes'
- Fix a large number of spelling mistakes
2022-01-13 07:57:56 -05:00
Vagrant Cascadian
5e7658925b drivers/usb/gadget/dwc2_udc_otg.c: Fix spelling of "resetting". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
0776c5fbb7 drivers/ddr/altera/sequencer.c: Fix spelling of "resetting". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
d1cab4f5f0 arch/arm/mach-keystone/ddr3.c: Fix spelling of "resetting". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
0580cd1636 drivers/core/of_addr.c: Fix spelling of "shouldn't". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
8c8bf4f17b common/fdt_support.c: Fix spelling of "shouldn't". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
f697addf8a drivers/net/fec_mxc.c: Fix spelling of "resetting". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
1107b062e5 cmd/Kconfig: Fix spelling of "resetting". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
9413e3a175 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c: Fix spelling of "resetting". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
a5c20f6b91 drivers/usb/musb/musb_udc.c: Fix spelling of "mismatch". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
70463798b2 drivers/mtd/ubispl/ubispl.c: Fix spelling of "mismatched". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
11872975fd arch/arm/mach-bcm283x/msg.c: Fix spelling of "Failed". 2022-01-13 07:57:49 -05:00
Sean Anderson
46ad7cef64 treewide: invaild -> invalid
Somewhere along the way, someone misspelt "invalid" and it got copied
everywhere. Fix it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-13 07:57:49 -05:00
Tom Rini
37b876359f Merge branch '2022-01-12-assorted-updates'
- Fix binman fake blob support to write outside source directory
- Azure now has stages in the pipeline
- Update to latest focal tag for containers in CI.
- Finish dropping LynxOS
- Add migration message for timer code
2022-01-13 07:34:27 -05:00
Mihai Sain
93ddc09da2 board: sama7g5ek: set blue led on at boot time
Set blue led on at boot time in order to highlight that u-boot is loaded.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-01-13 11:45:00 +02:00