This replaces debug() calls with printf() so that it is immediately
obvious from the console that something is wrong.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is a cosmetic patch that reorders variable definitions in the
inverse order of their line length, where possible.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
By convention, the eTSEC MDIO controller nodes are defined in DT at
0x2d24000 and 0x2d50000, but actually U-Boot does not touch the
interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM,
MDIO_EMAPM).
That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM,
MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at
the 0x520 offset.
So shift the DT-defined register map by the offset of MDIO_MIIMCFG when
mapping the MDIO bus registers.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The point of this patch is to eliminate the use of the locally-defined
"reg" variable (which interferes with next patch) and simplify the
fallback to the default CONFIG_SYS_TBIPA_VALUE in case "tbi-handle" is
missing.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Macb Ethernet controller requires a RX buffer of 128 bytes. It is
highly sub-optimal for Gigabit-capable GEM that is able to use
a bigger DMA buffer. Change this constant and associated macros
with data stored in the private structure.
RX DMA buffer size has to be multiple of 64 bytes as indicated in
DMA Configuration Register specification.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
DMA configuration was heavily dependent on the HW
defaults, add function to properly set the required
fields, including the new dma_burst_length.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
GEM support higher DMA burst writes/reads than the default (4).
add configuration structure with dma burst length so it could be
applied later to DMA configuration.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds support for the sgmii phy interface,
available only to DM users, dictated by current driver
design.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
macb.h provides macros for reading/setting bitfields,
in macb registers and descriptors. use that instead
of redefining them in the source file.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
add support for clock rates higher than 2.4Mhz
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Few registers and bits were added by Cadence and
they were not updated in the headers.
Take the latest definitions as defined in Linux
header (5.1) that also includes some comments
about existing registers.
One register was improperly named (UR), fix that.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This driver is used for MDIO muxes driven over I2C. This is currently
used on Freescale LS1028A QDS board, on which the physical MDIO MUX is
controlled by an on-board FPGA which in turn is configured through I2C.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Using 'phy_connect' instead of 'phy_find_by_mask' and 'phy_connect_dev'
both deduplicates code and adds support for 'fixed-link'.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
SGMII 2500 as supported on NXP SoCs requires AN to be disabled, handle
this case in the enetc sgmii init code.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Ethernet interfaces using serial protocols go through the serdes block
integrated in the SoC. This is accessed over dedicated internal MDIOs
which are part of the Ethernet PCI functions. Set up serdes at _start,
along with other protocol specific port/MAC configuration.
MDIO code is shared with enetc_mdio, read/write functions are exported
from fsl_enetc_mdio for this reason.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adds a driver for the MDIO interface currently integrated in LS1028A SoC.
This MDIO interface is shared by multiple ethernet interfaces and is
presented as a stand-alone PCI function on the SoC ECAM.
Ethernet has a functional dependency on MDIO, for simplicity there is a
single config option for both.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adds a driver for NXP ENETC ethernet controller currently integrated in
LS1028A. ENETC is a fairly straight-forward BD ring device and interfaces
are presented as PCI EPs on the SoC ECAM.
Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The designware eth driver registers an mdio bus during probe, but if no
PHY is found, this bus is never removed although probe failes and the
driver is shown as not probed in the dm tree.
This later leads to errors when e.g. the mii or mdio commands try to
use available mdio buses because the mdio bus is still registered but
all corresponding data structures are invalid because probe failed.
Fix this by unregistering the mdio bus on probe failure (just as it is
unregistered in the .remove callback, too).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adds a test using a makeshift MDIO MUX. The test is based on the existing
MDIO test. It uses the last emulated PHY register to verify MUX selection.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This 2nd register is used by the follow-up MDIO MUX test.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adds a class for MDIO MUXes, which control access to a series of
downstream child MDIOs.
MDIO MUX drivers are required to implement a select function used to switch
between child buses.
MUX children are registered as MDIO buses and they can be used just like
regular MDIOs.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current code fails to probe some C45 PHYs that also respond to C22 reads.
This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as
previously posted on the u-boot list).
If the PHY ID reads all 0s just ignore it and try the next devad.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX
phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and
LPA_1000XHALF bits.
Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If macb is gem and is gigabit capable, lpa value is not read from
the right register(MII_LPA) and is read from MII_STAT1000. This patch
fixes reading of the lpa value.
Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
Independent Interface (RMII), and the Management Data Input/Output (MDIO)
interface for physical layer device (PHY) management. The TI AM65x SoC has
integrated two-port Gigabit Ethernet Switch subsystem into device MCU
domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII
and RMII interfaces and an internal Communications Port Programming
Interface (CPPI) port (Host port 0).
Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX
channels and on RX channels operating by TI am654 NAVSS Unified DMA
Peripheral Root Complex (UDMA-P) controller.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use phys_addr_t for mdio_base address to avoid build
warnings on arm64 and dra7. Cast it to uintprt_t before
assigning to regs.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch is to use block layer to read from mmc in cortina
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Because all MSCC SoC use the same MDIO bus, put the implementation in
one common file(mscc_miim) and make all the other MSCC network drivers to
use these functions.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
A very simple test for DM_MDIO, mimicks a register write/read through the
sandbox bus to a dummy PHY.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
stand-alone devices. Useful in particular for systems that support
DM_ETH and have a stand-alone MDIO hardware block shared by multiple
Ethernet interfaces.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When serdes configuration was written in hardware there was a delay
of 100ms to be sure that configuration was written. But the delay is not
needed because already the function serdes_write it is checking that the
operation finished.
Therefore remove the mdelay. This improves the speed of configuring the
network driver.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The code block reading the DT property for the clock output control was
before the phy's DT node pointer was set, so it could never work. Move
it after the node pointer is set.
Also store the unsigned 32-bit property into an unsigned value, not a
signed value, as the former will cause a problem if value overflows.
For instance, if one were to add 0xffffffff as a code to mean the clock
output should be turned off.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Janine Hagemann <j.hagemann@phytec.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When not using DM_ETH, these PHY settings are programmed with default
values hardcoded into the driver. When using DM_ETH, they should come
from the device tree. However, if the device tree does not have the
properties, the driver will silent use -1. Which is entirely out of
range, programs nonsense into the PHY's registers, and does not work.
Change this to use the same defaults as non-DM_ETH if the device tree is
lacking the properties.
As an alternative, the kernel driver for the phy will display an error
message and fail if the device tree is lacking.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Janine Hagemann <j.hagemann@phytec.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJc+TqsAAoJEMrHeC97M/+miKwP/3OouX3slblEfUELRj/9qLlU
ypdUDKDQupGSrTIyhJHFdGbA2ct/ERl4mH/kU8NNeCHVCsdvrrmuw+k4jfVZfIyi
d9gWmU5WanNPzdWwdo0NrVNXjN5LPduxeUCYHdDEggDJuG3YL4LA9pPyrWpL8o8t
tLPr8YMB1u5Ab8Vn/1A9lKvmw98V59LmWVxZh0AtAdOTvWgEZQe1R5Vex+MHacnK
uR/Dm3ry5v7ZlR/kMZ0C+Ip1aw9GU4e+O+LCGlU4Jr0GV2XQOr4ehxWtN02nYubc
sYXbkW7UArR0I0g8YPXPoBI9PToi57bHW/TXKoI8yDIll7vZ9PDjT/FbUJM9rv72
WU6T7+K2DeHflmp4NljiesD2rDnti0XSCbe4o5o/jD+YkzH6YoJbco4nsae7TBSM
R3rgV7/+St7zC1IjFq0TUG+S9qSUmZqA4k66+j5/SS6pLQOW3dYemL0/up2cRX5w
dx00JTQkHyh7Q/GfH8r7yZqIToW9djB9HeT88ovPUCh8rVfDqNn8/WKd2JAfkxda
QiZDs49BMBsnWpK+vPqiq/suoJeSwDB70iMzrGgBg+mTd9eJcD0c5QBURYE0jm2H
GqQ04WNi8sLzULhMqKbBdPZhBMzyNmDXF6MC+y/OcUM5k8z6tY8LDro3wgHXWVpX
DLiFVbkHbLhlUJbeO8dD
=2C9f
-----END PGP SIGNATURE-----
Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-boot
- Add Ethernet support for STM32MP1
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
We should not access reserved register on i.MX8, otherwise met SERROR
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
with PHY Realtek RTL8211 (RGMII)
We also support some other PHY config on stm32mp157c
PHY_MODE (MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
At present the link speed change callback is a nop. According to
macb device tree bindings, an optional "tx_clk" is used to clock
the ethernet controller's TX_CLK under different link speed.
In 10/100 MII mode, transmit logic must be clocked from a free
running clock generated by the external PHY. In gigabit GMII mode,
the controller, not the external PHY, must generate the 125 MHz
transmit clock towards the PHY.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This updates DM version macb_linkspd_cb() signature for future
expansion, eg: adding an implementation for link speed changes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Move the main symbol for Freescale Fman Ethernet controller option to
Kconfig. Also migrate the CONFIG_SYS_QE_FMAN_FW_IN_xxx macros and
rename the SPIFLASH one to follow the same format as all of the others.
To do this fully we need to migrate CONFIG_QC, do so.
Signed-off-by: Tom Rini <trini@konsulko.com>
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
In mt7629-rfb.dts, the phy-handle is a reference to the node phy0, not the
node itself:
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
}
However the driver used ofnode_find_subnode("phy-handle") to read the node.
It will always fail.
This patch replaces ofnode_find_subnode with dev_read_phandle_with_args to
make sure the node can be read correctly.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This version of the RTL-8168 is present on some development boards and
is compatible with this driver. Add support for identifying this version
of the chip so that U-Boot won't complain about it being unknown.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Implement this callback that allows the MAC address to be set for the
Ethernet card. This is necessary in order for the device to be able to
receive packets for the MAC address that U-Boot advertises.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There is a need to fill node before clk_output_sel is setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Reviewed-by: <hannes.schmelzer@br-automation.com>
Commit d397f7c45b ("net: phy: micrel: Separate KSZ9000 drivers from
KSZ8000 drivers") separated the KSZ8xxx and KSZ90x1 drivers and warns
that you shouldn't select both of them due to a device ID clash between
the KSZ9021 and the KS8721, asserting that "it is highly unlikely for a
system to contain both a KSZ8000 and a KSZ9000 PHY". Unfortunately
boards like the SAMA5D3xEK do contain both types of PHY, but fortunately
the Linux Micrel PHY driver provides a solution by using different PHY
ID and mask values to distinguish these chips.
This commit contains the following changes:
- The PHY ID and mask values for the KSZ9021 and the KS8721 now match
those used by the Linux driver.
- The warnings about not enabling both drivers have been removed.
- The description for PHY_MICREL_KSZ8XXX has been corrected (these are
10/100 PHYs, not GbE PHYs).
- PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 no longer select PHY_GIGE
since this is selected by PHY_MICREL_KSZ90X1.
- All of the relevant defconfig files have been updated now that
PHY_MICREL_KSZ8XXX does not default to 'Y'.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In some of the device trees that specify skew values for KSZ90x1 PHYs
the values are stored (incorrectly) in the MAC node, whereas in others
it is in an 'ethernet-phy' subnode. Previously the code would fail to
find and program these skew values, so this commit changes it to look
for an "ethernet-phy" subnode first, and revert to looking in the MAC
node if there isn't one.
The device trees affected (where the skew values are in a subnode) are
imx6qdl-icore-rqs.dtsi, r8a77970-eagle.dts, r8a77990-ebisu.dts,
r8a77995-draak.dts, salvator-common.dtsi, sama5d3xcm.dtsi,
sama5d3xcm_cmp.dtsi, socfpga_cyclone5_vining_fpga.dts,
socfpga_stratix10_socdk.dts and ulcb.dtsi. Before this change the skew
values in these device trees would be ignored.
The device trees where the skew values are in the MAC node are
socfpga_arria10_socdk.dtsi, socfpga_arria5_socdk.dts,
socfpga_cyclone5_de0_nano_soc.dts, socfpga_cyclone5_de10_nano.dts,
socfpga_cyclone5_de1_soc.dts, socfpga_cyclone5_is1.dts,
socfpga_cyclone5_socdk.dts, socfpga_cyclone5_sockit.dts. These should be
unaffected by this change.
The changes were tested on a sama5d3xcm.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit ff7bd212cb ("net: phy: micrel: fix divisor value for KSZ9031
phy skew") fixed the skew value divisor for the KSZ9031, but left the
code using the same divisor for the KSZ9021, which is incorrect.
The preceding commit c16e69f702 ("net: phy: micrel: add documentation
for Micrel KSZ90x1 binding") added the DTS documentation for the
KSZ90x1, changing it from the equivalent file in the Linux kernel to
correctly state that for this part the skew value is set in 120ps steps,
whereas the Linux documentation and driver continue to this day to use
the incorrect value of 200 that came from the original KSZ9021 datasheet
before it was corrected in revision 1.2 (Feb 2014).
This commit sorts out the resulting confusion in a consistent way by
making the following changes:
- Update the documentation to be clear about what the skew values mean,
in the same was as for the KSZ9031.
- Update the Micrel PHY driver to select the appropriate divisor for
both parts.
- Adjust all the device trees that state skew values for KSZ9021 PHYs to
use values based on 120ps steps instead of 200ps steps. This will result
in the same values being programmed into the skew registers as the
equivalent device trees in the Linux kernel do, where it incorrectly
uses 200ps steps (since that's where all these device trees were copied
from).
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
For AQR405 in register 4.c441 bit 15 was override with 0. This caused the
phy to not negotiate at 2.5GB rate with mac. To avoid
this override it needed first to know the previous value of reg 4.c441
and set only bit 3.
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
