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3 commits

Author SHA1 Message Date
Shengzhou Liu
e04f9d0c2f board/freescale: Update ddr clk_adjust
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:06:57 -07:00
Shengzhou Liu
aa7a2226b5 armv8/ls2080ardb: Update DDR timing to support more UDIMMs
Optimize DDR timing for good margins to support new Transcend
and Apacer DDR4 UDIMM besides current Micron UDIMM.

Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
following UDIMM on LS2080ARDB.
 - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
 - Apacer UDIMM: 78.C1GM4.AF10B
 - Transcend UDIMM: TS1GLH72V1H

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17 09:26:59 -07:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Renamed from board/freescale/ls2085ardb/ddr.h (Browse further)