Commit graph

31017 commits

Author SHA1 Message Date
Bhuvanchandra DV
508f412125 arm: vf610: Add iomux support for DSPI
Add iomux definitions for DSPI second instance.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:55 +02:00
Bhuvanchandra DV
098d85840e arm: vf610: Add clock support for DSPI
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:55 +02:00
Bhuvanchandra DV
30748d81d0 colibri_vf: Enable GPIO support
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:55 +02:00
Bhuvanchandra DV
a7b1808ee3 colibri_vf: Add pinmux entries for GPIOs
Inorder to use the pins as GPIO, apart from setting the alt-function,
pinmuxing need to be done, this patch adds pinmux entries of
few GPIOs.

Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:55 +02:00
Bhuvanchandra DV
d348a943e7 dm: gpio: vf610: Add GPIO driver support
Add GPIO driver support to Freescale VF610

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:54 +02:00
Bhuvanchandra DV
ae89bb0d36 dm: gpio: uclass: Add flag to control sequence numbering
Like SPI and I2C few GPIO controllers also have
multiple chip instances. This patch adds the
flag 'DM_UC_FLAG_SEQ_ALIAS' in gpio_uclass driver
to control device sequence numbering. By defalut
the dev->r_seq for gpio_uclass will alwalys
returns -1, which leads the gpio driver probe
failure when using the driver with device trees.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:54 +02:00
Fabio Estevam
cd6ddc4813 mx6_common: Fix LOADADDR and SYS_TEXT_BASE for MX6SL and MX6SX
Commit 8183058188 ("imx6: centralise common boot options in
mx6_common.h") broke boot on mx6sl and mx6sx by assuming that all mx6
SoCs use the same LOADADDR/SYS_TEXT_BASE range, which is not correct.

DDR on mx6sx/mx6sl starts at 0x80000000.

Adjust LOADADDR/SYS_TEXT_BASE to the proper values for mx6sx/mx6sl,
so that these SoCs can boot again.

Also, TQMA6 requires a custom CONFIG_SYS_TEXT_BASE value, so move
its setting prior to the inclusion of mx6_common.h.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
2015-06-08 08:35:59 +02:00
Fabio Estevam
9a8804a85e wandboard: Add board revision detection support
There are two revisions of wandboard: version B1 and C1.

Add the revision detection support, so that the correct dtb file can
be automatically loaded.

Based on the patch from Richard Hu <hakahu@gmail.com>.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-By: Vagrant Cascadian <vagrant@aikidev.net>
2015-06-08 08:34:38 +02:00
Nikhil Badola
19b17d1254 drivers: usb: fsl: Return if USB_MAX_CONTROLLER_COUNT is incorrect
Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller
to be initialised is incorrect

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
2015-06-07 15:46:02 +02:00
Hans de Goede
5bcec545a6 image-fit: Fix compiler warning in fit_conf_print()
This fixes the following compiler warning:

In file included from tools/common/image-fit.c:1:0:
./tools/../common/image-fit.c: In function ‘fit_conf_print’:
./tools/../common/image-fit.c:1470:27: warning: logical not is only applied
 to the left hand side of comparison [-Wlogical-not-parentheses]
    (const char **)&uname) > 0;

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-06-06 09:30:20 -04:00
Tom Rini
290ac3bb1a Merge git://git.denx.de/u-boot-sunxi 2015-06-06 07:03:07 -04:00
Hans de Goede
277af820b5 sunxi: Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default
Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then
needing to have this in every sunxi defconfig file.

This also fixes the Merrii_A80_Optimus defconfig no longer building.

Cc: Maxin B. John <maxin.john@enea.com>
Reported-by: Maxin B. John <maxin.john@enea.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-06-05 21:09:14 +02:00
Hans de Goede
348cce20ef sunxi: Add a proper dts file for the ga10h a33 based tablet
Add and use a proper dts for the ga10h a33 based tablet, as
submitted upstream.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-06-05 21:09:14 +02:00
Tom Rini
f1737152c0 Merge git://git.denx.de/u-boot-fdt 2015-06-05 12:14:01 -04:00
Tom Rini
d85cd29133 Merge git://git.denx.de/u-boot-dm 2015-06-05 11:21:08 -04:00
Paul Kocialkowski
3c4c142e5d fdt: Documentation for a few support functions aside their prototypes
This instroduces comments that explain the purpose, parameters and return codes
of a few fdt support functions, that are used to fill the fdt.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-05 08:32:58 -06:00
Paul Kocialkowski
10be5b5d3a fdt: Pass the device serial number through devicetree
Before device-tree, the device serial number used to be passed to the kernel
using ATAGs (on ARM). This is now deprecated and all the handover to the kernel
should now be done using device-tree. Thus, this passes the serial-number
property to the kernel using the serial-number property of the root node, as
expected by the kernel.

The serial number is a string that somewhat represents the device's serial
number. It might come from some form of storage (e.g. an eeprom) and be
programmed at factory-time by the manufacturer or come from identification
bits available in e.g. the SoC.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Simon Glass <sgj@chromium.org>
2015-06-05 08:32:07 -06:00
Hans de Goede
373a6cb381 sunxi: Rename Astar_MID756 to Et_q8_v1_6 to match kernel dts name
Rename the Astar_MID756 to Et_q8_v1_6 to match the kernel dts name.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-06-04 14:12:07 +02:00
Hans de Goede
8b1ba94151 sunxi: Sync dts files with the linux kernel
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2 ,
this gives us a proper dtsi file for the A33 rather then abusing
sun8i-a23.dtsi for this.

And this replaces our minimal (dummy) sun7i-a20-mk808c and
sun8i-a33-astar-mid756 dts files with proper ones.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-06-04 14:12:03 +02:00
Hans de Goede
a52783e11d sunxi: gpio: Add "allwinner,sun8i-a33-pinctrl"
Add "allwinner,sun8i-a33-pinctrl", this is used by the latest upstream
linux sunxi dts files.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-06-04 14:11:55 +02:00
Hans de Goede
2c23da06ba sunxi: Add new Mele_A1000G_quad defconfig
The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been
using the same defconfig (and dts on the kernel side) for both models.
Unfortunately this does not work for the otg controller, on the M9 this
is routed to a micro-usb connector on the outside, while as on the
A1000G-quad it is connected to an usb to sata bridge.

This commit adds a new defconfig for the Mele-A1000G-quad to allow using
different otg controller settings on the 2 boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-06-04 14:11:23 +02:00
Hans de Goede
7afebb5b29 sunxi: usb_phy: Swap check for disconnect threshold
Before this commit the code for determining the disconnect threshold was
checking for sun4i or sun6i assuming that those where the exception and
that newer SoCs use a disconnect threshold of 2 like sun7i does.

But it turns out that newer SoCs actually use a disconnect threshold of 3
and sun5i and sun7i are the exceptions, so check for those instead.

Here are the settings from the various Allwinner SDK sources:
 sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
 sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
 sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
 sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
 sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
 sun8i-h3:  USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
 sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);

Note this commit makes no functional changes for sun4i - sun7i, and
changes the disconnect threshold for sun8i to match what Allwinner uses.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-06-04 14:11:01 +02:00
Hans de Goede
1c09fa38e0 sunxi: mmc: Enable pull-up on card-detect gpio pin
On some boards we need to enable the internal pull-up te reliable detect
that no card is inserted.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-06-04 14:08:28 +02:00
Masahiro Yamada
d9a607f2bd gpio: fix typos in GPIO header
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-06-04 03:38:05 -06:00
Simon Glass
b14d547245 sandbox: Compile test device tree when CONFIG_UT_DM is defined
A conflict between the PMIC and unit test work means that the sandbox test
device tree file is no-longer built. Fix this.

Series-to: u-boot
Series-cc: joe, prz

Change-Id: I6616428e05713e5306f848e7dd0a645dedf0934e
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:34:48 -06:00
Simon Glass
52d3bc5d18 sandbox: dts: Add the real-time-clock test nodes back in
These were lost when the PMIC series was applied. Add them back so that the
tests pass again.

Reported-by: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-04 03:34:47 -06:00
Simon Glass
f4d84576a4 sandbox: dts: Sort the sandbox.dts file
Sort this by node name for easier browsing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:34:47 -06:00
Simon Glass
171e991d17 sandbox: dts: Sort the test.dts file a little
There are some core test nodes near the beginning of the file which should
be grouped together. But for other nodes, let's sort them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-04 03:34:47 -06:00
Simon Glass
4e389366e8 dm: Sort the uclass IDs after the tegra/PMIC addition
Tidy up the sort order again.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-04 03:34:47 -06:00
Simon Glass
2bb02e4fe2 dm: pci: Allow PCI bus numbering aliases
Commit 9cc36a2 'dm: core: Add a flag to control sequence numbering' changed
the default uclass behaviour to not support bus numbering. This is incorrect
for PCI and that commit should have enabled the flag for PCI.

Enable it so that PCI buses can be found and the 'pci' command works again.
Also add a test for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:34:47 -06:00
Simon Glass
8939df092e sandbox: Tidy up terminal restore
For some reason 'u-boot -D' does not restore the terminal correctly when
the 'reset' command is used. Call the terminal restore function explicitly
in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-04 03:34:47 -06:00
Gabriel Huau
5d3c2c542d x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:32:23 -06:00
Gabriel Huau
5318f18d2c x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:32:08 -06:00
Andrew Bradford
afbbd413a3 x86: baytrail: pci region 3 is not always mapped to end of ram
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up.  There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
5c564226fc x86: qemu: Implement PIRQ routing
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
f2653e8dd9 x86: coreboot: Control I/O port 0xb2 writing via device tree
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
683b09d783 x86: qemu: Create separate i440fx and q35 device trees
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
65cdd9be3e x86: coreboot: Fix cosmetic issues
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:17 -06:00
Bin Meng
d04e30b839 x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSP
FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:17 -06:00
Bin Meng
6c4247e98e tools: ifdtool: Do not write region while its size is negative
We should ignore those regions whose size is negative. These are
typically optional and unused regions (like GbE and platform data).

Change-Id: I65ad01746144604a1dc0588b617af21f2722ebbf
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:02:57 -06:00
Bin Meng
4be2f42bbc x86: qemu: Adjust VGA initialization
As VGA option rom needs to run at C segment, although QEMU PAM emulation
seems to only guard E/F segments, for correctness, move VGA initialization
after PAM decode C/D/E/F segments.

Also since we already tested QEMU targets to differentiate I440FX and Q35
platforms, change to locate the VGA device via hardcoded b.d.f instead of
dynamic search for its vendor id & device id pair.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:40 -06:00
Bin Meng
0fcb7acf67 x86: qemu: Enable legacy IDE I/O ports decode
QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix
driver does sanity check to see whether legacy ports decode is turned on.
To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
cc7debc719 x86: qemu: Turn on legacy segments decode
By default the legacy segments C/D/E/F do not decode to system RAM.
Turn on the decode via Programmable Attribute Map (PAM) registers
so that we can write configuration tables in the F segment.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
5466983200 x86: qemu: Make host bridge (b.d.f=0.0.0) visible
The default weak version of pci_skip_dev() in drivers/pci/pci_common.c
skips the host bridge (b.d.f = 0.0.0) which is actually the i440fx/q35
chipset for QEMU targets. Define CONFIG_PCI_CONFIG_HOST_BRIDGE to make
it visible in the PCI configuration space.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Andrew Bradford
1dc03c2639 x86: fsp_support: Correct high mem comment typo
High mem starts at 4 GiB.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
67b24970ce x86: Do sanity test on pirq table before writing
If pirq_routing_table points to NULL, that means U-Boot fails to
generate the table before in create_pirq_routing_table(), so we
test it against NULL before actually writing it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
05b98ec346 x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
5910955f3c x86: Document irq router device tree bindings
Describe all required properties needed by the irq router device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
9c7dea602e x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
2aa3a7fb1c x86: qemu: Add ATA/SATA support
Enable legacy IDE support on the pc target and AHCI support on the
q35 target. Default configuration is to support the pc target.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00