Commit graph

18 commits

Author SHA1 Message Date
Tom Rini
65cc0e2a65 global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:08 -05:00
Paweł Anikiel
e26ecebc68 socfpga: arria10: Allow dcache_enable before relocation
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea4519 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:15 +08:00
Tien Fong Chee
4720b83d2c arm: socfpga: arria10: Enable double peripheral RBF configuration
Double peripheral RBF configuration are needed on some devices or boards
to stabilize the IO configuration system.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17 12:58:01 +08:00
Tien Fong Chee
3b4ee40f20 arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF
This patch triggers warm reset to recover the MPFE NoC from corruption
due to high frequency transient clock output from HPS EMIF IOPLL at
VCO startup after peripheral RBF is programmed.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17 12:58:01 +08:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Ley Foon Tan
db5741f7a8 arm: socfpga: Convert system manager from struct to defines
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get system manager base address from DT node instead of
using #define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Marek Vasut
72c347ced8 ARM: socfpga: Add support for selecting bridges in bridge command
Add optional "mask" argument to the SoCFPGA bridge command, to select
which bridges should be enabled/disabled. This allows the user to avoid
enabling bridges which are not connected into the FPGA fabric. Default
behavior is to enable/disable all bridges.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:56 +02:00
Ang, Chee Hong
877ec6ebbd arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20 17:12:25 +01:00
Marek Vasut
0b8f6378cb ARM: socfpga: Reorder Arria10 SPL
The Arria10 SPL is a complete mess of calls to functions which are
called in the wrong context and it is surprise it works at all. This
patch tries to clean that mess up by shuffling the function calls
around and moving the calls into the correct context. Due to the
delicate nature of the reordering, this is done in one huge patch.

The following changes happen in this patch:
- Security policy init and NIC301 happens first in board_init_f()
- The clock init happens very early in board_init_f() in SPL only
- arch_early_init_r() only registers the FPGA, just like on Gen5
- arch_early_init_r() is never called from any _f() function
- Dedicated FPGA pins are inited in board_init_f() as on Gen5

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24 12:05:20 +02:00
Marek Vasut
d6a61da462 ARM: socfpga: Remove adhoc ethernet reset and configuration
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
f9edeb32a9 ARM: socfpga: Zap all the UART handling complexity
The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-08-13 22:35:40 +02:00
Marek Vasut
42f4b83b52 ARM: socfpga: Init missing security policies on A10
The Arria10 requires proper configuration of the NOC firewall, otherwise
the access to certain areas of the LWHPS bridge fails in Linux. Add the
missing setup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-25 00:13:32 +02:00
Ley Foon Tan
2e1de5bd97 arm: socfpga: Add do_bridge_reset for Arria 10
Add do_bridge_reset() function for Arria 10, it is required by misc.c.

arch/arm/mach-socfpga/built-in.o: In function `do_bridge':
arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset'
make[1]: *** [u-boot] Error 1

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12 09:22:12 +02:00
Tien Fong Chee
011fa5f33d ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot
SoC FPGA info is required in both SPL and U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18 10:30:47 +02:00
Marek Vasut
32f99757f4 ARM: socfpga: Repair A10 EMAC reset handling
The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Ley Foon Tan
35b9800ff2 arm: socfpga: Add misc support for Arria 10
Add misc support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18 11:33:18 +02:00