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105 commits

Author SHA1 Message Date
Stefan Roese
07b7b0037a [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.

For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-06 07:47:04 +01:00
Stefan Roese
0238898382 [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board
This code will optimize the DDR2 controller setup on a board specific
basis.

Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05 10:38:05 +01:00
Marian Balakowicz
8318fbf8cc Fix sequoia separate object direcory building problems. 2006-10-23 22:17:05 +02:00
Stefan Roese
a73c8dbb43 Update NAND boot documentation
Patch by Stefan Roese, 12 Sep 2006
2006-09-12 08:49:07 +02:00
Stefan Roese
887e2ec9ec Add support for AMCC Sequoia PPC440EPx eval board
- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
  in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
  please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
  in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006
2006-09-07 11:51:23 +02:00