Commit graph

2881 commits

Author SHA1 Message Date
Shengzhou Liu
074596c0b5 armv8/ls1043: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17 09:26:19 -07:00
Simon Glass
c649e3c91c dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSI
This option currently enables both the command and the SCSI functionality.
Rename the existing option to CONFIG_SCSI since most of the code relates
to the feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Stefan Agner
1fb5133395 imx: iomux-v3: fix UART input selects
Several UART input selects are missing. The fourth input select
for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
(at least in Rev. B of the i.MX 7Dual Reference Manual). However,
when looking at the tables of other input selects, it is very natural
that there must be an input select for the UART2_TX_DATA_ALT0 pad.
The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
it was required to set that particular input select register to get a
working UART2.
2016-05-17 17:52:20 +02:00
Eric Nelson
9f623326eb imx: mx6: mx6sl_pins: add GPIO variant for SD1_DAT5
This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
2016-05-17 17:52:19 +02:00
Andre Przywara
1ea4fac5a3 arm/arm64: Move barrier instructions into separate header
Commit bfb33f0bc4 ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.

Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.

This fixes compilation for 64-bit sunxi boards (Pine64).

Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-05-12 11:13:03 -04:00
Stephen Warren
d9b6f58efd ARM: tegra: enable GPU node by compatible value
In current Linux kernel Tegra DT files, 64-bit addresses are represented
in unit addresses as a pair of comma-separated 32-bit values. Apparently
this is no longer the correct representation for simple busses, and the
unit address should be represented as a single 64-bit value. If this is
changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no
longer be able to find and enable the GPU node, since it looks up the node
by name.

Fix that function to enable nodes based on their compatible value rather
than their node name. This will work no matter what the node name is, i.e
for DTs both before and after any rename operation.

Cc: Thierry Reding <treding@nvidia.com>
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-05-04 13:31:03 -07:00
Nishanth Menon
e52e334e5c ARM: DRA7: Add ABB setup for all domains
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25 15:10:41 -04:00
Nishanth Menon
a818097a33 ARM: OMAP5: Enable ABB configuration for MM voltage domain
Since we setup the voltage and frequency for the MM domain, we *must*
setup the ABB configuration needed for the domain as well. If we do not
do this, kernel configuring just the frequency using the default boot
loader configured voltage can fail on many corner lot units.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25 15:10:40 -04:00
Nishanth Menon
3708e78c33 ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structure
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.

Hence, move the txdone mask definition over to structure describing
voltage domain.

Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25 15:10:39 -04:00
Nishanth Menon
2d9d057be6 ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2
This information is already available under vcores->volts.efuse.reg.
There is no reason for duplicating the information since AVS Class 0
definitions are common for OMAP5 and DRA7 and defined with
STD_FUSE_OPP_* macros. This allows a central location of defining
the ABB and voltage definitions especially since they are reused.

This also makes it simpler to prevent mistakes involved when changing
the boot OPP for the device.

Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25 15:10:38 -04:00
Tom Rini
89cb2b5f8b configs: Re-sync with cmd/Kconfig
Update the config.h and defconfig files for the commands that 8e3c036
converted over to Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:09:47 -04:00
Tom Rini
78d1e1d0a1 configs: Re-sync almost all of cmd/Kconfig
This syncs up the current cmd/Kconfig and include/configs/ files with the
only exception being CMD_NAND.  Due to how we have used this historically
we need to take further care here when converting.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:09:40 -04:00
Tom Rini
588d269ffe Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-04-25 13:34:42 -04:00
Fabio Estevam
9999fc0957 MX6UL: Add definition for UART6 base address
Define the UART6_BASE_ADDR for MX6UL.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-04-19 16:36:54 +02:00
Akshay Bhat
90d7cc42b3 imx: mx6: Fix procedure to switch the parent of LDB_DI_CLK
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.

To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.

This patch was ported from the 3.10.17 NXP kernel
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d

NXP errata number: ERR009219, EB821

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2016-04-19 16:05:12 +02:00
Lokesh Vutla
bd716dd03d ARM: AM43xx: Fix BOOT_DEVICE_USB ID
commit 62c5674ea1 ("omap: SPL boot devices cleanup and completion")
cleans up the boot device ids for amx3xx soc. But mistakenly updates wrong
device IDs for AM43xx USB. Fixing the same here.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-18 17:11:44 -04:00
Tom Rini
814013253f Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-04-13 07:19:50 -04:00
Vogt, Christof
7f961c90d7 am33xx changed BOOT_DEVICE_SPI to correct value
Changed BOOT_DEVICE Code for SPI on AM33xx.
According AM335x reference manual page 4960
(SPRUH73L-October 2011-Revised February 2015)
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-04-11 20:48:24 -04:00
Purna Chandra Mandal
f968467785 arm: add missing writes[bwql], reads[bwql].
ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-04-10 17:18:41 +02:00
Tom Rini
43d3fb5c06 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-04-06 14:17:22 -04:00
York Sun
3c1d218a1d armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-06 10:26:46 -07:00
Vincent Siles
96077896ee arm: ls102xa: Fix order of CSU indexes in ns_access.h
This patch aims to fix the order of CSU slave index for the LS1021a
board.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-04-06 10:26:21 -07:00
Ed Swarthout
70e21b0642 armv8: LSCH2 early and final mmu needs matching NS attribute
When switching between the early and final mmu tables, the stack will
get corrupted if the Non-Secure attribute is different.  For ls1043a,
this issue is currently masked because flush_dcache_all is called
before the switch when CONFIG_SYS_DPAA_FMAN is defined.

Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-04-06 08:35:09 -07:00
Stefan Roese
9fc56631a4 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU
Currently only chip-select 0 is supported by the kirkwood SPI driver.
The Armada XP / 38x SoCs also use this driver and support multiple chip
selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-04-06 15:38:56 +02:00
Siarhei Siamashka
d96ebc468d sunxi: Add support for Allwinner A64 SoCs
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.

Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Chen-Yu Tsai
93bac95310 sunxi: clk: Fix USB PHY clock macros for A83T
The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-31 17:04:08 +02:00
Tom Rini
0badc648dc Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-03-29 12:58:45 -04:00
Rai Harninder
ed2530d096 armv8/ls2080ardb: Enable VID support
This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.

Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Mingkai Hu
d91721d4ac armv8: fsl-layerscape: Add LS1023A SVR
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Mingkai Hu
16cee52138 armv8: fsl-layerscape: Fix LS1043A SVR register
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Saksham Jain
4a97a0c91d armv8: fsl-lsch3: Disable SMMU during secure boot
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.

For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:22 -07:00
Saksham Jain
809d343a1a armv8: ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:21 -07:00
Saksham Jain
bef238cb1e armv8: ls2080: Change env variable "fdt_high"
"fdt_high" env variable was set to 0xcfffffff for secure boot.
Change it to 0xa0000000 for LS2080 to be consistent with non-secure
boot targets.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:21 -07:00
Saksham Jain
3f701cc50a armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDR
To unify steps for secure boot for xip (eg. NOR) and non-xip memories
(eg. NAND, SD), bootscipts and its header are copied to main memory.
Validation and execution are performed from there.

For other ARM Platforms (ls1043 and ls1020), to avoid disruption of
existing users, this copy step is not used for NOR boot.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:21 -07:00
Saksham Jain
216e93a185 armv8: ls2080: Add bootscript header addr for secure boot
During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it executes. This requires a header for bootscript.

When secure boot is enabled, default bootcmd is changed to first
validate bootscript using the header and then execute the script.

For ls2080, NOR memory map is different from other ARM SoCs. So a new
address on NOR is used for this bootscript header (0x583920000). The
Bootscript address is mentioned in this header along with addresses of
other images.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:21 -07:00
Saksham Jain
fcfdb6d580 armv8: ls2080rdb: ls2080qds: Add secure boot support
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).

Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:20 -07:00
Saksham Jain
fd6dbc98a7 armv8: fsl-lsch3: Add new header for secure boot
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.

Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:20 -07:00
Saksham Jain
2827d64774 armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFG
Add configs for various IPs used during secure boot. Add address
and endianness for SEC and Security Monitor. SRK are fuses in SFP
(fuses for public key's hash). These are stored in little endian
format.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:19 -07:00
Saksham Jain
3808190af0 armv8: ls2080: Add SFP Configs for LS2080
In LS2080, SFP has version 3.4. It is in little endian. The base
address is 0x01e80200. SFP is used in Secure Boot to read fuses.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:19 -07:00
Peng Fan
e1bed80272 dm: i2c: mxc_i2c: implement i2c_idle_bus
Implement i2c_idle_bus in driver, then setup_i2c can
be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL.
The i2c_idle_bus force bus idle flow follows setup_i2c in
arch/arm/imx-common/i2c-mxv7.c

This patch is an implementation following linux kernel patch:
"
commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5
Author: Gao Pan <b54642@freescale.com>
Date:   Fri Oct 23 20:28:54 2015 +0800

    i2c: imx: implement bus recovery

    Implement bus recovery methods for i2c-imx so we can recover from
    situations where SCL/SDA are stuck low.

    Once i2c bus SCL/SDA are stuck low during transfer, config the i2c
    pinctrl to gpio mode by calling pinctrl sleep set function, and then
    use GPIO to emulate the i2c protocol to send nine dummy clock to recover
    i2c device. After recovery, set i2c pinctrl to default group setting.
"

See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed
description.
1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus.
2. Discard the __weak attribute for i2c_idle_bus and implement it,
   since we have pinctrl driver/driver model gpio driver. We can
   use device tree, but not let board code to do this.
3. gpio state for mxc_i2c is not a must, but it is recommended. If
   there is no gpio state, driver will give tips, but not fail.
4. The i2c controller was first probed, default pinctrl state will
   be used, so when need to use gpio function, need to do
   "pinctrl_select_state(dev, "gpio")" and after force bus idle,
   need to switch back "pinctrl_select_state(dev, "default")".

This is example about how to use the gpio force bus
idle function:
"
 &i2c1 {
 	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
	status = "okay";
	[....]
 };

[.....]

	pinctrl_i2c1_gpio: i2c1grp_gpio {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
		>;
	};
"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
2016-03-28 09:22:58 +02:00
Lokesh Vutla
37217f0e0a ARM: asm: types: Introduce DMA_ADDR_T_64BIT
dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
addresses, dma_addr_t need only be 32 bits wide.  Bus addresses, e.g., PCI BARs,
may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
kernel virtual addresses, so they don't care about the size of the actual
bus addresses.
Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
DMA still use 32bit address like in case of DRA7 and Keystone platforms.

This is inspired from the Linux kernel types implementation[1]

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142

Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:13:03 -04:00
Alexander Graf
d990f5c834 arm: Add support for HYP mode and LPAE page tables
We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.

So this patch introduces support for both long descriptor PTEs and HYP mode
registers.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-27 09:12:17 -04:00
Alexander Graf
53eb45ef40 arm64: Add 32bit arm compatible dcache definitions
We want to be able to reuse device drivers from 32bit code, so let's add
definitions for all the dcache options that 32bit code has.

While at it, fix up the DCACHE_OFF configuration. That was setting the bits
to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless
bits and make the index explicit.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-27 09:12:16 -04:00
Nishanth Menon
c755e67516 ARM: OMAP5/DRA7: Expose do_set_iodelay
do_set_iodelay can now be used from board files based on needs of the
platforms variation they have.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:15 -04:00
Nishanth Menon
ceb7d77d6f ARM: OMAP5/DRA7: Split iodelay functionality into sub steps
Since many platforms may need different pad configuration required
depending on variation of the platform with minor deltas, it is
easier to maintain a sub step based approach to allow for pin mux
and iodelay configuration which may depend on the platform variations
and need to be done in IO isolation.

While we retain the older __recalibrate_iodelay function which provides
a ready sequencing, __recalibrate_iodelay_start and
__recalibrate_iodelay_end may be alternatively used now and the callers
will be responsible for the correct sequencing of operations.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:15 -04:00
Ravi Babu
d851ad3a66 ARM: DRA72x: Add support for detection of SR2.0
Add support for detection of SR2.0 version of DRA72x family of
processors.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:12 -04:00
Vikas Manocha
adcc90b401 stm32f746-disco: enable flash support
This patch enables embedded flash for stm32f746 discovery board.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-03-26 18:49:28 -04:00
Vikas Manocha
9ecb0c416c stm32: stm32f4: move flash driver to mtd driver location
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-03-26 18:49:28 -04:00
Stefan Roese
51560f0b04 arm: mx6: Add UART8 base address for i.MX6UL
Add the base address for the i.MX6UL so that this UART can be used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-03-26 14:16:12 +01:00
Tom Rini
a6164205ee Merge git://www.denx.de/git/u-boot-marvell 2016-03-25 12:57:18 -04:00
Leonid Iziumtsev
f7440928e6 mx27: 16-bit wide watchdog registers
Make the watchdog registers 16-bit wide, as they are according to TRM.

Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-25 14:03:28 +01:00
Stefan Roese
84d6919118 arm: mvebu: spi.h: Add registers for direct write access
The direct write config register is needed for SPI direct write mode
configuration.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:48:07 +01:00
Hans de Goede
fc8991c61c sunxi: Fix gmac not working due to cpu_eth_init no longer being called
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.

This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().

The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.

Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
2016-03-23 22:04:13 +01:00
Chen-Yu Tsai
70fe24ed93 sunxi: Support SID e-fuses on A83T and H3
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-23 22:04:13 +01:00
Shengzhou Liu
dd8e740c78 driver/ddr/fsl: Add workaround for erratum A-009803
During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Stuart Yoder
7e7e126470 pci/layerscape: add defines for LUT
The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
that maps PCI requester IDs (bus/dev/fun) to a stream ID.

Add defines for the register offsets.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Stuart Yoder
029a407dae armv8: ls2080a: update stream ID partitioning info
Update comments around how stream IDs are partitioned.
Stream IDs allocated to PCI are no longer divided up by
controller, but are instead a contiguous range

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:12 -07:00
Alison Wang
b2f3addbb2 arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
As the compatible property values for QSPI and DSPI dts nodes
are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
need to be updated too.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:11 -07:00
Shaohui Xie
abc7d0f75c armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Prabhakar Kushwaha
2b690b9837 armv8: lsch3: Enable WUO config for RNI-20 node
Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.

WRIOP IP is connected to RNI-20 Node.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Stefano Babic
312a6c016a Merge branch 'next' 2016-03-20 22:04:29 +01:00
Nishanth Menon
3eb80d10c7 ARM: DRA7: DDR: Enable SR in Power Management Control
If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 21:30:19 -04:00
Alexander Graf
7985cdf74b arm64: Remove non-full-va map code
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:10 -04:00
Alexander Graf
d473f0c621 thunderx: Move mmu table into board file
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:02 -04:00
Alexander Graf
5e2ec773bb arm64: Make full va map code more dynamic
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:01 -04:00
Alexander Graf
9bb367a590 arm64: Disable TTBR1 maps in EL1
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:00 -04:00
Alexander Graf
0691484ac1 thunderx: Calculate TCR dynamically
Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:12:59 -04:00
Paul Kocialkowski
faec3f9841 omap4: Reboot mode support
Reboot mode is written to SAR memory before reboot in the form of a string.

This mechanism is supported on OMAP4 by various TI kernels.

It is up to each board to make use of this mechanism or not.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:53 -04:00
Paul Kocialkowski
6e495a453f omap4: Properly enable USB PHY clocks
This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:50 -04:00
Paul Kocialkowski
3ef56e61c8 omap-common: Rename set_muxconf_regs_essential to set_muxconf_regs
There is no distinction between essential and non-essential mux configuration,
so it doesn't make sense to have an "essential" prefix.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:06 -04:00
Paul Kocialkowski
ed5ddebe96 omap4: Export jedec sdram timings
Individual boards might provide their own emif_get_device_timings function and
use the jedec timings in their own way, hence those have to be exported.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:32 -04:00
Paul Kocialkowski
96703acd0a omap4: Export elpidia sdram timings
Individual boards might provide their own emif_get_device_timings function and
use the elpidia timings in their own way, hence those have to be exported.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:31 -04:00
Paul Kocialkowski
7cb998ba85 omap4: Export elpidia sdram device details
Individual boards might provide their own emif_get_device_details function and
use elpidia device details in their own way, hence those have to be exported.

This also wraps existing definitions with the proper ifdef logic.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:30 -04:00
Paul Kocialkowski
90ca5dfec4 omap3: Use a define for reboot reason offset
This introduces a define for the offset to the reboot reason, rather than
hardcoding it.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 15:10:48 -04:00
Paul Kocialkowski
c5412b084b omap3: String-based reboot mode handling
This switches reboot mode handling to a string-based interface, that allows more
flexibility to set a common interface with the next generations of OMAP devices.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 15:10:47 -04:00
Tom Rini
4d339a9e8a Merge branch 'master' of git://git.denx.de/u-boot-video 2016-03-15 08:01:17 -04:00
Lokesh Vutla
29c20ba235 ARM: DRA7: emif: Enable interleaving for higher address space
Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:47 -04:00
Lokesh Vutla
e3ce3aa103 ARM: DRA7: emif: Check for enable bits before updating leveling output
Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:47 -04:00
Kipisz, Steven
d88d6c8ccf ARM: OMAP4/5: Add generic board detection hook
Many TI EVMs have capability to store relevant board information
such as DDR description in EEPROM. Further many pad configuration
variations can occur as part of revision changes in the platform.
In-order to support these at runtime, we for a board detection hook
which is available for override from board files that may desire to do
so.

NOTE: All TI EVMs are capable of detecting board information based on
early clocks that are configured. However, in case of additional needs
this can be achieved within the override logic from within the board
file.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:34 -04:00
Lokesh Vutla
0bea813d00 ARM: omap-common: Add standard access for board description EEPROM
Several TI EVMs have EEPROM that can contain board description information
such as revision, DDR definition, serial number, etc. In just about all
cases, these EEPROM are on the I2C bus and provides us the opportunity
to centralize the generic operations involved.

The on-board EEPROM on the BeagleBone Black, BeagleBone, AM335x EVM,
AM43x GP EVM, AM57xx-evm, BeagleBoard-X15 share the same format.
However, DRA-7* EVMs, OMAP4SDP use a modified format.

We hence introduce logic which is generic between these platforms
without enforcing any specific format. This allows the boards to use the
relevant format for operations that they might choose.

This module will compile for all TI SoC based boards when
CONFIG_TI_I2C_BOARD_DETECT is enabled to have optimal build times for
platforms that require this support.

It is important to note that this logic is fundamental to the board
configuration process such as DDR configuration which is needed in
SPL, hence cannot be part of the standard u-boot driver model (which
is available later in the process). Hence, to aid efficiency, the
eeprom contents are copied over to SRAM scratchpad memory area at the
first invocation to retrieve data.

To prevent churn with cases such as DRA7, where eeprom format maybe
incompatible, we introduce a generic common format in eeprom which
is made available over accessor functions for usage.

Special handling for BBG1 EEPROM had to be introduced thanks to the
weird eeprom rev contents used.

The follow on patches introduce the use of this library for AM335x,
AM437x, and AM57xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:33 -04:00
Kipisz, Steven
725700dcbf ARM: OMAP4/5: Centralize gpi2c_init
Centralize gpi2c_init into omap_common from the sys_proto header so
that the information can be reused across SoCs.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:32 -04:00
Kipisz, Steven
93e6253d11 ARM: OMAP4/5: Centralize early clock initialization
Early clock initialization is currently done in two stages for OMAP4/5
SoCs. The first stage is the initialization of console clocks and
then we initialize basic clocks for functionality necessary for SoC
initialization and basic board functionality.

By splitting up prcm_init and centralizing this clock initialization,
we setup the code for follow on patches that can do board specific
initialization such as board detection which will depend on these
basic clocks.

As part of this change, since the early clock initialization
is centralized, we no longer need to expose the console clock
initialization.

NOTE: we change the sequence slightly by initializing console clocks
timer after the io settings are complete, but this is not expected
to have any functioanlity impact since we setup the basic IO drive
strength initialization as part of do_io_settings.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:32 -04:00
Simon Glass
73223f0e1b Kconfig: Move CONFIG_FIT and related options to Kconfig
There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.

Move these options to Kconfig and tidy up board configuration:

   CONFIG_FIT
   CONFIG_OF_BOARD_SETUP
   CONFIG_OF_SYSTEM_SETUP
   CONFIG_FIT_SIGNATURE
   CONFIG_FIT_BEST_MATCH
   CONFIG_FIT_VERBOSE
   CONFIG_OF_STDOUT_VIA_ALIAS
   CONFIG_RSA

Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.

Note: Masahiro's moveconfig.py script is amazing.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:07 -04:00
Jacob Chen
8530783594 rockchip: video: Add LVDS support in vop driver
LVDS have a different display out mode, add code to get right flag.

The vop_ip decide display device and the remote_vop_id decide which
vop was being used. So we should use the remote_vop_id to set DCLK_VOP.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-14 22:24:10 +01:00
Jacob Chen
35ac89dd8f rockchip: video: Add a display driver for rockchip LVDS
Some Rockchip SoCs support LVDS output. Add a display driver for this so
that these displays can be used on supported boards.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-14 22:06:33 +01:00
Simon Glass
9e971632cd freescale: Remove CONFIG_DM from header files
Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP
relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA.
Remove the hacks which enable CONFIG_DM in header files and update the
defconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 14:21:27 -04:00
Fabio Estevam
e25a0656ba mx7: Distinguish between dual and solo versions
Read the number of cores in the fuses to distinguish between
the dual and solo versions.

Tested on a mx7d sabresd and on a mx7solo warp7.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-03-09 12:50:39 +01:00
Bhuvanchandra DV
fc9e8f2817 colibri-vf: Disable pull-up configuration in GPIO pin mux
During very early boot-ROM execution the pinmux
configuration isi in Hi-Z state. If pull-up is enabled
on GPIO pad's there will be a short period of toggle
from high to low on the IO when GPIO is set low during
boot. To avoid this glitch, disable pull-up configuration
in GPIO pinmux.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2016-03-02 14:47:16 +01:00
Masahiro Yamada
f8facbe71e gpio: do not include <asm/arch/gpio.h> for UniPhier
I implemented a GPIO driver based on Driver Model for the UniPhier
SoC family, but I could not find any good reason why such SoC
specific GPIO headers are needed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-29 03:50:15 +09:00
Tom Rini
e1417c7b66 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-02-24 18:44:15 -05:00
Vikas Manocha
e66c49fa93 stm32: add support for stm32f7 & stm32f746 discovery board
This patch adds support for stm32f7 family & stm32f746 board.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-02-24 18:43:57 -05:00
Vikas Manocha
09959ba3c5 gpio: stm32_gpio: move base addresses to the soc file
Base addresses for GPIOs could be different for different socs, this
patch moves the base addresses from driver to the soc specific location.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-02-24 18:42:50 -05:00
Vikas Manocha
14cec06113 gpio: stm32_gpio: move clock config from driver to board
This patch removes the gpio clock enable from gpio driver & move it in the
board code, making it possible to use the gpio driver with other socs.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-02-24 18:42:49 -05:00
Alison Wang
a08b1921b4 armv7: ls102xa: Move smmu and stream id initialization into the common soc code
The initialization for smmu and stream id is moved into the common soc
code.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:15 -08:00
Mingkai Hu
bbc8e053ba armv8/ls1043a: Implement workaround for erratum A009660
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:40:56 -08:00
Shengzhou Liu
3e0a0fbbac armv8/ls1043a: enable workaround for errarum A009942
DDR erratum A-009942 applies to LS1043A.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:40:56 -08:00
Tom Rini
52dd704bf8 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2016-02-23 15:35:47 -05:00
Jelle van der Waa
dc44fd8ae4 sunxi: H3: Add support for the host usb-phys
Add support for phy 1-3.

Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-02-23 20:59:10 +01:00
Michal Simek
e832a142b9 ARM: zynq: Remove unused SPI base addresses
Remove unused macros. Adresses are taken from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
2016-02-22 16:20:59 +01:00
Tom Rini
595af9db24 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-02-21 07:56:16 -05:00
Peng Fan
83703a1ccf imx: mx7: implement functions to boot auxiliary core
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
0623d375cf imx: mx6: implement functions to boot auxiliary core
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
af0135928e imx: mx7d: Add RDC support
Add the peripherals/masters definitions and registers base addresses
for mx7d RDC.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
d08607e1e7 imx: mx6sx Add RDC mappings of masters and peripherals
Add the definitions for the RDC mappings for i.MX6 SoloX.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
de09c43bbf imx: imx-common: introduce Resource Domain Controller support
Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
613e01065a imx: mx6: introduce rdc regs
Introudce rdc regs structure and rdc sema reg structure for i.MX6.
For now, to i.MX6, only i.MX6SX supports this.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:25 +01:00
Ulises Cardenas
f91e65a74e imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7
Refactored data structure for CAAM's job ring and Secure Memory
to support i.MX7.

The new memory map use macros to resolve SM's offset by version.
This will solve the versioning issue caused by the new version of
secure memory of i.MX7

Signed-off-by: Ulises Cardenas <raul.casas@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-02-21 11:20:54 +01:00
Simon Glass
e007633b00 tegra: video: Clean up the old LCD/PWM driver code
Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we
are using driver model for video.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:53 -07:00
Simon Glass
bfda03770c tegra: video: Move LCD enums into the driver
There is no need to have these in a separate file as they are not
referenced from anywhere else.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:53 -07:00
Simon Glass
9e6866d3b6 tegra: video: Convert tegra20 LCD driver to driver model
Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.

Boards which use this are fixed up, but only seaboard is tested.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:52 -07:00
Simon Glass
ce0c474a72 tegra: video: Merge the two config structures together
We have a structure for the display panel and another for the controller.
There is some overlap between them. Merge them to simplify the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:52 -07:00
Simon Glass
71cafc3fba tegra: video: Merge the display driver into one file
At present we have code in arch/arm and code in drivers/video. Move it all
into drivers/video since it is a display driver and our current approach is
to put all driver code in drivers/.

Make a few functions static now that they are not used outside the file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:52 -07:00
Simon Glass
4dd811581a tegra: lcd: Merge tegra124-lcd.c into display.c
There isn't a lot of benefit of have two separate files. With driver model
the code needs to be in the same driver, so it's better to have it in the
same file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:51 -07:00
Simon Glass
7429b9623b tegra: pwm: Add a driver for the tegra PWM
This PWM supports four channels. The driver always uses the 32KHz clock,
and adjusts the duty cycle accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:50 -07:00
Tom Rini
823ecd72bb Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-02-14 08:39:32 -05:00
Masahiro Yamada
494456bc67 spl: define BOOT_DEVICE_USB
This enum is referenced from common/spl/spl.c.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Siva Durga Prasad Paladugu
78cb965af0 zynqmp: nand: Add Nand driver support for zynqmp
Add nand driver support for zynqmp. The Nand
controller used in ZynqMP is Arasan Nand Flash
controller.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[scottwood: Fix checkpatch warning]
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-12 17:27:28 -06:00
Vikas Manocha
dffceb4b15 serial: serial_stm32: move clock config from driver to board
This patch removes the uart clock enable from serial driver & move it in the
board code.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-08 10:10:36 -05:00
Ye Li
d4d1dd6749 mx6: soc: Add ENET2 mac address support
The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
MAC address from fuse for ENET2.

Signed-off-by: Ye Li <ye.li@nxp.com>
2016-02-02 21:03:59 +01:00
Marek Vasut
d339f16911 arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-02 20:58:46 +01:00
Tom Rini
008e61f512 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-02-02 06:51:05 -05:00
Ashish kumar
7711cc0a06 arm8: ls2080: Move the core errata defines out of board specific file
Valid for core A57

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-01 13:59:55 -08:00
Ashish kumar
2ea3a448cc armv8: ls2080a: Implement workaround for core errata 829520, 833471
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.

833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-01 13:58:22 -08:00
Marek Vasut
8890c2fbe6 arm: Remove S bit from MMU section entry
Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
2016-01-31 16:32:56 +01:00
Marek Vasut
a592e6fb7f arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7
The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured for the
cache on ARMv7 to operate correctly.

The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
issues which are hard to replicate, for example certain USB sticks are not
detected or QSPI NOR sometimes fails to write pages completely.

The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
correct because the code which added the test(s) for CONFIG_ARMV7 was added
shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
not adjusted correctly to reflect that change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
2016-01-31 16:32:56 +01:00
Tom Rini
cd85bec36d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-01-27 15:05:36 -05:00
Qianyu Gong
b0f20caf65 armv8/ls1043aqds: add QSPI boot support
Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:29:09 -08:00
Aneesh Bansal
0a6b2714ad secure_boot: create function to determine boot mode
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:42 -08:00
Aneesh Bansal
bdc22074c5 secure_boot: split the secure boot functionality in two parts
There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
         validating and booting LINUX.

For ESBC phase, there is no difference in SoC's based on ARM or
PowerPC cores.

But the exit conditions after ISBC phase i.e. entry conditions for
U-Boot are different for ARM and PowerPC.
PowerPC:

If Secure Boot is executed, a separate U-Boot target is required
which must be compiled with a diffrent Text Base as compared to
Non-Secure Boot. There are some LAW and TLB settings which are
required specifically for Secure Boot scenario.

ARM:
ARM based SoC's have a fixed memory map and exit conditions from
BootROM are same irrespective of boot mode (Secure or Non-Secure).

Thus the current Secure Boot functionlity has been split into
two parts:
CONFIG_CHAIN_OF_TRUST
This will have the following functionality as part of U-Boot:
1. Enable commands like esbc_validate, esbc_halt
2. Change the environment settings based on bootmode, determined
   at run time:
     - If bootmode is non-secure, no change
     - If bootmode is secure, set the following:
         - bootdelay = 0 (Don't give boot prompt)
         - bootcmd = Validate and execute the bootscript.

CONFIG_SECURE_BOOT
This is defined only for creating a different compile time target
for secure boot.

Traditionally, both these functionalities were defined under
CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement
for a separate Secure Boot target for ARM based SoC's.
CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be
determine at run time.

Another Security Requirement for running CHAIN_OF_TRUST is that
U-Boot environemnt must not be picked from flash/external memory.
This cannot be done based on bootmode at run time in current U-Boot
architecture. Once this dependency is resolved, no separate
SECURE_BOOT target will be required for ARM based SoC's.

Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is
defining CONFIG_ENV_IS_NOWHERE

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:32 -08:00
Aneesh Bansal
74eecd820f secure_boot: include/configs: move definition of CONFIG_CMD_BLOB
CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was
earlier defined in all config files. The definition has been
moved to a common file which is included by all configs.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:26 -08:00
Aneesh Bansal
ef6c55a240 secure_boot: include/configs: make secure boot header file uniform
The file fsl_secure_boot.h must be included in config file for
Secure Boot. This is not required to be protected by any macro.
CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be
turned on.

The above was missing in some config files and all files have been
made uniform in this respect.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:08 -08:00
Michal Simek
af813acd48 ARM64: zynqmp: Add support for SD1 boot mode
SD1 boot mode is using different bootmode values.
Add support for this mode used on DC1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Siva Durga Prasad Paladugu
0a5bcc8c0d ARM64: zynqmp: Modify the SD and QSPI bootmode values
Modify the SD bootmode value to 0x3 as per latest
spec. Also add new boot mode QSPI 32 bit boot mode

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
0785dfd8a7 ARM64: zynqmp: Use the same U-Boot version with/without ATF
Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Vishnu Patekar
f3ad64c88c sunxi: Add support for LPDDR3 for A83T
Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T.
Mostly the timing parameters are different from DDR3.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Vishnu Patekar
f5fd8caf7f sunxi: Groundwork to support new dram type for A83T
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3,
Allwinner Homlet v1.2 has DDR3.

This adds groundwork to support for new DRAM type for A83T.

Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must
be set in respective board defconfig.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Chen-Yu Tsai
ed80584f30 sunxi: Support H3 CCU security switches
H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.

Configure them to enable non-secure access.

For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Chen-Yu Tsai
5823664fb8 sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3
Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.

Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.

This patch supports the new settings, and sets them to allow non-secure
access.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:04 +01:00
Pratiyush Mohan Srivastava
aa4ba7f7a2 armv8: ls2040a: Add support of LS2040A SoC
Freescale's LS2040A is a another personality of LS2080A SoC
without AIOP support consisting of 4 armv8 cores.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:17 -08:00
Shaohui Xie
c238ad0a33 armv8: fsl-layerscape: fixes lsch2 serdes registers define
Fixes lsch2 SerDes registers define according to LS1043A RM Rev D.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:16 -08:00
Shengzhou Liu
a994b3deb0 driver/ddr/fsl: Add workaround for A009663
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Shengzhou Liu
0d3972cfcd fsl/ddr: Add workaround for ERRATUM_A009942
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:14 -08:00
Peng Fan
d9699de85c imx: mx7: default enable MDIO open drain
The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:15:14 +01:00
Peng Fan
9ba18ff8ef imx: mx6ul/sx: fix mmdc_ch0 clk calculation
Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.

Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:13:21 +01:00
Peng Fan
234dc63301 imx: mx6: add more entry for mxc_ccm_reg
Add more entries for structure mxc_ccm_reg.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:12:27 +01:00
Peng Fan
bedaa842ae imx: nand: update GPMI NAND driver to support MX7
Update GPMI NAND driver and BCH head file to support i.MX7

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:09:32 +01:00
Peng Fan
1fc4f80495 imx: apbh_dma: Update APBH-DMA for MX7D
Update APBH-DMA driver and head files to support i.MX7D

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:09:16 +01:00
Simon Glass
dae594f210 rockchip: spl: Support full-speed CPU in SPL
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
affd4a9fa0 rockchip: Tidy up the register-access macros
These work reasonable well, but there are a few errors:

- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
7b7ad5c31c rockchip: video: Add a video-output driver
Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
5852d539ea rockchip: video: Add a display driver for rockchip eDP
Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
c253948341 rockchip: video: Add a display driver for rockchip HDMI
Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.

Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
009741fbae rockchip: Rename the CRU_MODE_CON fields
These should match the datasheet naming. Adjust them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
0e23fd81a5 pwm: rockchip: Add a PWM driver for Rockchip SoCs
Add a simple driver which implements the standard PWM uclass interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
64b7faa7f9 rockchip: clock: Add a function to find a clock by ID
The current approach of using uclass_get_device() is error-prone. Another
clock (for example a fixed-clock) may cause it to break. Add a function that
does a proper search.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Simon Glass
a4275f5e52 rockchip: Convert the PMU IOMUX registers into an array
This is easier to deal with when using generic code since it allows us to
use a register index instead of naming each register.

Adjust it, adding an enum to improve readability.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Jelle van der Waa
9d0826879e sunxi: Add support for the I2C controller which is part of the PRCM
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: Minor cleanups]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

applied with fixing 2 checkpatch warnings:
WARNING: please, no space before tabs

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-01-21 07:30:01 +01:00
Heiko Schocher
1d48ca69e5 arm, ubifs: fix gcc5.x compiler warning
compiling U-Boot for openrd_base_defconfig with
gcc 5.x shows the following warning:

  CC      fs/ubifs/super.o
In file included from fs/ubifs/ubifs.h:35:0,
                 from fs/ubifs/super.c:37:
fs/ubifs/super.c: In function 'atomic_inc':
./arch/arm/include/asm/atomic.h:55:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
  local_irq_save(flags);
  ^
fs/ubifs/super.c: In function 'atomic_dec':
./arch/arm/include/asm/atomic.h:64:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
  local_irq_save(flags);
  ^
  CC      fs/ubifs/sb.o
[...]
  CC      fs/ubifs/lpt.o
In file included from include/linux/bitops.h:123:0,
                 from include/common.h:20,
                 from include/ubi_uboot.h:17,
                 from fs/ubifs/ubifs.h:37,
                 from fs/ubifs/lpt.c:35:
fs/ubifs/lpt.c: In function 'test_and_set_bit':
./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
  local_irq_save(flags);
  ^
  CC      fs/ubifs/lpt_commit.o
In file included from include/linux/bitops.h:123:0,
                 from include/common.h:20,
                 from include/ubi_uboot.h:17,
                 from fs/ubifs/ubifs.h:37,
                 from fs/ubifs/lpt_commit.c:26:
fs/ubifs/lpt_commit.c: In function 'test_and_set_bit':
./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
  local_irq_save(flags);
  ^
  CC      fs/ubifs/scan.o
  CC      fs/ubifs/lprops.o
  CC      fs/ubifs/tnc.o
In file included from include/linux/bitops.h:123:0,
                 from include/common.h:20,
                 from include/ubi_uboot.h:17,
                 from fs/ubifs/ubifs.h:37,
                 from fs/ubifs/tnc.c:30:
fs/ubifs/tnc.c: In function 'test_and_set_bit':
./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized]
  local_irq_save(flags);
  ^
  CC      fs/ubifs/tnc_misc.o

Fix it.

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-01-20 10:03:58 -05:00
Sergey Temerkhanov
a5b9fa30ce armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure
This commit adds functions issuing calls to secure monitor or
hypervisore. This allows using services such as Power State
Coordination Interface (PSCI) provided by firmware, e.g. ARM
Trusted Firmware (ATF)

The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this

Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
2016-01-19 22:25:36 +00:00
Sergey Temerkhanov
94f7ff36e5 armv8: New MMU setup code allowing to use 48+ bits PA/VA
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
2016-01-19 22:25:36 +00:00
Sergey Temerkhanov
ba5648cd91 armv8: Add read_mpidr() function
This patch adds the read_mpidr() function which returns the
MPIDR_EL1 register value

Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>

Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-19 22:25:35 +00:00
Tom Rini
5b8031ccb4 Add more SPDX-License-Identifier tags
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 08:31:21 -05:00
Vladimir Zapolskiy
1222305b55 arm: lpc32xx: switch SPL builds to driver model
For NXP LPC32xx boards the change enables SPL_DM option, this allows
to use any driver model UART driver in SPL images, hence a restriction
on HSUART in SPL image is removed and well as definitions for non-DM
NS16550 driver, its DM version is used instead.

Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE
for LPC32xx boards.

The change adds about 5KB to the resulting SPL image (for devkit3250
board SPL image is increased from 10672 to 15608 bytes).

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-13 21:05:22 -05:00
Vladimir Zapolskiy
d25ba89e8b arm: lpc32xx: switch serial console to driver model
On NXP LPC32xx platform for non-SPL builds the change adds
standard (NS16550) and high-speed UARTs to driver model.
Due to specific of DM NS16550 device description UART clock can not be
got in runtime and by default it is set to 13MHz, if board PERIPH_CLK
is different, this should be specified in board configuration file.

For SPL builds HSUARTs are disabled and non-DM NS16550 driver is
compiled, if needed.

The change also updates default configs of devkit3250 and work_92105
boards to reflect updates in platform files.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-13 21:05:22 -05:00
Tom Rini
f1993ca066 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-01-03 10:32:24 -05:00
Michael Heimpold
fe21eaf92d ARM: mxs: allow boards to select DC-DC switching clock source
For some board designs, it might be useful to switch the DC-DC
clock source to something else rather the default 24 MHz, e.g.
for EMI reasons.

For this, override the mxs_power_setup_dcdc_clocksource function
in your board support files.

Example:
void mxs_power_setup_dcdc_clocksource(void)
{
    mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ);
}

Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-01-03 15:56:36 +01:00
Mingkai Hu
0d6faf2bd0 armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Mingkai Hu
2949ae5212 armv8/fsl_lsch2: fix DCSR_DCFG address
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Tom Rini
e6e3faa5c2 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-12-14 20:27:23 -05:00
Tang Yuantian
989c5f0a8f armv8: Add sata support on Layerscape ARMv8 board
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:35 +08:00
Aneesh Bansal
9711f52806 armv8/ls1043ardb: add SECURE BOOT target for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:35 +08:00
York Sun
c107c0c05c armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
Yao Yuan
6c4a1eba3f armv7/fsl-ls102xa: Workaround for DDR erratum A008514
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:32 +08:00
Yao Yuan
762b353546 arm: ls102xa: enable all the snoop signal for masters.
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Yao Yuan
7ba0261810 arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Shaohui Xie
e994dddbbe armv8/ls1043ardb: Add support for >2GB memory
This patch also expose the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Shengzhou Liu
0c028a0328 arm: ls102x: add get_svr and IS_SVR_REV helper
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
Kamil Lulko
665624149a stm32: Convert serial driver to DM
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-12 15:56:08 -05:00
vishnupatekar
81f50d93cb sunxi: Add support for Allwinner A83T DRAM
Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to dram helper in future.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:47 +01:00
vishnupatekar
f542948b1e sunxi: clk: add basic clocks for A83T
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:47 +01:00
vishnupatekar
d5a3357f1b sunxi: Add support for UART0 in PB pin group on A83T
On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 11:14:21 +01:00
Hans de Goede
cbc1a91afb sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.

Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Chen-Yu Tsai <wens@csie.org>
2015-12-10 11:14:16 +01:00
Peng Fan
0c890879fe imx: mx6: fix reg base address when runtime usage
Should use parenthese to wrap the macro definition, otherwise
we will encounter error like the following:

"
if (base_addr != LCDIF1_BASE_ADDR) {
    puts("Wrong LCD interface!\n");
    return -EINVAL;
}
"

Without this patch, we will always encounter "Wrong LCD interface".

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-12-07 15:03:08 +01:00
Michal Simek
d9ae52c8f0 zynq: sdhci: Move driver to DM
Move driver to DM

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:29 +01:00
Michal Simek
769afa54c6 ARM: zynq: Remove unused SERIAL macros for serial_zynq
Remove unused macros when driver was moved to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Kamil Lulko
5be9356926 Change e-mail address of Kamil Lulko
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
2015-12-05 18:22:32 -05:00
Tom Rini
a85670e40d Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-12-04 08:21:28 -05:00
huang lin
53c45f0ca2 rockchip: add rk3036 sdram driver
add rk3036 sdram driver so we can set up sdram in SPL

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
07d8d35a61 rockchip: add early uart driver
add early uart driver so we can print debug message in
SPL stage

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
c17736c02a rockchip: rk3036: Add header files for GRF
GRF is the gereral register file. Add header files with register definitions.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
3f2ef13924 rockchip: rk3036: Add clock driver
Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
cc2244b8fa rockchip: add timer driver
some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Tom Rini
1670c8c219 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-11-30 15:18:30 -05:00
York Sun
3785f57015 armv8: fsl-layerscape: Fix early MMU table for nand boot
The early MMU table doesn't enable all addresses. Unused addresses
are marked as invalid, as introduced by commit 9979922. An entry
was missing for NAND flash space, causing nand boot failure.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2015-11-30 09:11:13 -08:00
Prabhakar Kushwaha
b401736463 armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
Alison Wang
d764129d30 armv8/layerscape: Update MMU table with execute-never bits
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
2015-11-30 09:11:11 -08:00
York Sun
61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
7023100971 armv8/ls1043ardb: add USB support
Add support for the third USB controller for LS1043A.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Shaohui Xie
02b5d2ed86 armv8/ls1043aqds: add LS1043AQDS board support
LS1043AQDS Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 DIMM
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two RGMII ports
 * XFI 10G port
 * SGMII
 * QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Mingkai Hu
af523a0d56 pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00