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4 commits

Author SHA1 Message Date
Marc Ferland
9452d58e10 arm: dart6ul: enable DM_ETH for the dart6ul
This patch converts the dart6ul ethernet support to DM_ETH and cleans
up the legacy ethernet code. The clean up, more specifically:

* moves the fec2 node and pin definition to the carrier board DTS
  since the phy associated with it is on the carrier board and not on
  the SoM;
* add the reset pin associated to each phy;
* separate the ethernet, mdio and reset pins of each fec so that they
  are easier to reference;
* add clock properties to the phy nodes since they are connected to the
  50Mhz ENET[12]_TX_CLK clock of the SoC;
* remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty.

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
2021-01-23 11:30:31 +01:00
Marc Ferland
37648b600c arm: dart6ul: read and print SoM info from eeprom on startup
The dart6ul has an i2c eeprom at 0x50 which contains, among other
things, the manufacturing/revision/options info of the SoM. This patch
replaces the current checkboard() implementation with a more
exhaustive one based on the content of the eeprom.

Since this code uses the new driver model, some changes were also
required in the DTS to make the nodes related to i2c available before
relocation.

This code was inspired from the supported u-boot code from Variscite
which can be found here:

https://github.com/varigit/uboot-imx/tree/imx_v2018.03_4.14.78_1.0.0_ga_var02

New output example:

Board: PN: VSM-6UL-705B, Assy: AS1812142257, Date: 2019 Feb 17
       Storage: eMMC, Wifi: yes, DDR: 1024 MiB, Rev: 2.4G

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-12-26 14:56:09 +01:00
Marc Ferland
d4d7b663b8 arm: dart6ul: change compatible string for eeprom
The eeprom at address 0x50 is a BR24G04NUX-3TTR. It has a
4Kbit (512x8) capacity, change the compatible string to reflect this
fact.

Also, add an alias to easily refer to this eeprom with
fdt_path_offset() which will be in another commit.

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-12-26 14:56:09 +01:00
Parthiban Nallathambi
d8d33b6d4d imx: Add variscite DART-6UL Evaluation Kit
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite
DART-6UL iMX6ULL SoM.

CPU:   Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial@02020000
Out:   serial@02020000
Err:   serial@02020000
Net:   FEC0

Working:
 - Eth0
 - i2c
 - MMC/SD
 - eMMC
 - USB host
 - UART 1

Note: LCDIF porting needs DM_VIDEO
https://lists.denx.de/pipermail/u-boot/2019-April/365506.html

Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
2019-04-25 19:16:24 +02:00