Commit graph

13 commits

Author SHA1 Message Date
Pragnesh Patel
4ef196ce20 sifive: fix palmer's email address
Fix Palmer's email address

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-26 15:50:15 +08:00
Simon Glass
eb41d8a1be common: Drop linux/bug.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
0914011310 command: Remove the cmd_tbl_t typedef
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.

Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.

This requires quite a few header-file additions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 18:36:55 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Jagan Teki
286bcdb40f sifive: fu540: Enable spi-nor flash support
HiFive Unleashed A00 support is25wp256 spi-nor flash,
So enable the same and add test result log for future
reference.

Tested on SiFive FU540 board.

Thanks to Sagar for various use cases and tests.

[QUAD mode in dt with spi-tx-bus-width: <4>]
 pp opcode      = 0x34 [QUAD MODE]
 read opcode  = 0x6c  [QUAD MODE]
 erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

[SPI MODE in dt with spi-tx-bus-width: <1>]
pp opcode     = 0x12 [SPI MODE]
read opcode  = 0xc   [SPI MODE]
erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30 22:34:20 +05:30
Sagar Shrikant Kadam
b332a89799 configs: fu540: enable gpio driver
Enable the DM based GPIO driver for FU540-C000 SoC.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-18 09:04:08 +08:00
Sagar Shrikant Kadam
cba0635386 riscv: sifive: fu540: set serial environment variable from otp
This patch sets the serial# environment variable by reading the
board serial number from the OTP memory region.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:29:54 +08:00
Bhargav Shah
0b96a761c5 riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
This patch enables SiFive SPI and MMC SPI drivers for the
SiFive Unleashed board.

Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-19 14:25:06 +08:00
Anup Patel
9f2a0c0f38 riscv: sifive: fu540: Setup ethaddr env variable using OTP
This patch extends SiFive FU540 board support to setup ethaddr
env variable based on board serialnum read from OTP.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:52 +08:00
Anup Patel
8633edeb2a clk: sifive: Drop GEMGXL clock driver
The GEMGXL clock driver is now directly part of Cadence MACB
ethernet driver in upstream Linux kernel. There is no separate
GEMGXL clock driver in upstream Linux kernel hence we drop
GEMGXL clock driver from U-Boot as well.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Bin Meng
776d39d9a1 riscv: sifive: fu540: Enable GEMGXL MGMT driver
Enable the new GEMGXL MGMT driver so that GEM 10/100 Mbps works now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-06-01 13:33:17 -05:00
Lukas Auer
0ed93a8c59 riscv: fu540: enable SMP
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Anup Patel
3fda0262c3 riscv: Add SiFive FU540 board support
This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00