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3 commits

Author SHA1 Message Date
Codrin Ciubotariu
aae0e68909 drivers: net: vsc9953: Add LAG support
You can now configure LAG on VSC9953's ports using the command:
ethsw [port <port_no>] aggr {[help] | show | <lag_group_no>}

A port must belong to a single LAG. By default, a port
belongs to a LAG equal to the port's number.

For each frame, a hash will be calculated based on
Source/Destination MAC addresses, Source/Destination IP(v4/v6)
addresses, Source/Destination ports. This hash will be used to
select a single egress port from LAG. This also assures
that frames from the same flow will always have the
same egress port.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:19 -06:00
Codrin Ciubotariu
3507cf7f4a doc: t1040-l2switch: Update README
The driver for VSC9953 L2 switch IP supports many features and
the documentation needs to be updated.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:11 -06:00
Codrin Ciubotariu
6706b115a6 net/vsc9953: Add driver for Vitesse VSC9953 L2 Switch IP
This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP
is integrated in Freescale T1040 and T1020 SoCs.
The L2 switch has 10 Ethernet ports: 2 internal fixed-links
(ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps.
The external ports may be connected to PHYs over QSGMII and SGMII.

Commands have also been added to enable/disable a port and to
check a port's link speed, duplexity and status. The commands are:

ethsw port <port_nr> enable|disable - enable/disable an l2 switch port
ethsw port <port_nr> show - show an l2 switch port's configuration

port_nr=0..9; use "all" for all ports

For more detailse please see doc/README.t1040-l2switch

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:32:38 -08:00