Commit graph

50 commits

Author SHA1 Message Date
Ruchika Gupta
028dbb8db1 fsl_sec : Change accessor function to take care of endianness
SEC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of SEC IP.

So update acessor functions with common SEC acessor functions to take care
both type of endianness.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:16:50 -07:00
Tang Yuantian
ce249d956c powerpc/t104xrdb: support deep sleep in SPI/SD boot
Add deep sleep support in SPI/SD boot. The destination address
second stage uboot image is loaded to is changed because
currently this address will be used by kernel which means
we can't reserve it for resume.

Entry point to kernel is still placed in second stage uboot.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-12 12:26:47 -07:00
Shengzhou Liu
605714f669 powerpc/85xx: add fdt_fixup_dma3
On some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is
chosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:53 -07:00
Sandeep Singh
377ffcfabf powerpc/mpc85xx: Add workaround to enable TDM on T1040
This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Masahiro Yamada
8e2615752e bd_info: remove bi_barudrate member from struct bd_info
gd->bd->bi_baudrate is a copy of gd->baudrate.

Since baudrate is a common feature for all architectures,
keep gd->baudrate only.

It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
2014-05-12 15:19:45 -04:00
Codrin Ciubotariu
d616fc58e5 powerpc/cpu/mpc85xx: Add MAC address for layer 2 switch
T1040RDB and T1040QDS boards have an integrated l2 switch.
The switch needs a MAC address for Layer 2 protocols
(MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add
a MAC in device-tree, under node l2switch.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Scott Wood
8d451a7129 powerpc/85xx: Fix e6500 L2 cache stash IDs
The value written to L2CSR1 didn't match the value written to the
device tree.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Laurentiu TUDOR
51abee64ee powerpc/85xx: fix broken cpu "clock-frequency" property
When indexing freqProcessor[] we use the first
value in the cpu's "reg" property, which on
new e6500 cores IDs the threads.
But freqProcessor[] should be indexed with a
core index so, when fixing "the clock-frequency"
cpu node property, access the freqProcessor[]
with the core index derived from the "reg' property.
If we don't do this, last half of the "cpu" nodes
will have broken "clock-frequency" values.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
Prabhakar Kushwaha
e982746844 powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2
CHASSIS2 architecture never defines type of L2 cache present in SoC.
 it is dependent upon the core present in the SoC.
 for example,
    - e6500 core has L2 cluster (Kibo)
    - e5500 core has Backside L2 Cache

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
Николай Пузанов
e6394e9e8f Fix for incorrect conversion hex string to number (FMAN firmware address).
Signed-off-by: Николай Пузанов <punzik@gmail.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 11:51:26 -07:00
Prabhakar Kushwaha
997399fa42 powerpc: Fix CamelCase checkpatch warnings
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
because of this code checkpatch script generates "WARNING: Avoid CamelCase".

Convert variables name to normal naming convention and modify board, driver
files with updated the new structure.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:57:51 -07:00
York Sun
cb93071bb6 mpc85xx: Base emulator support
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Andy Fleming
7dd09b546d 85xx: Change clock-frequency compatible to 2.0
Accidentally applied an earlier version of the patch, which set
the compatible to "fsl,qoriq-clockgen-2", lacking the final
".0".

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-06-20 13:51:04 -05:00
Tang Yuantian
7b700d2125 powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen node
For T4/B4, the clockgen node compatible string is updated to version 2.
Add clock-frequency setting for this new version.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:43 -05:00
Dongsheng.wang@freescale.com
f5c2623d80 powerpc/mpc85xx: add setting of clock-frequency for mpic node
Set the device tree property associated with the mpic source
frequency. The frequency is used for mpic timer.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:42 -05:00
Kim Phillips
8aa5ec6e16 common/fdt_support.c: sparse fixes
trivial:

fdt_support.c:89:64: warning: Using plain integer as NULL pointer
fdt_support.c:325:65: warning: Using plain integer as NULL pointer
fdt_support.c:352:65: warning: Using plain integer as NULL pointer

For the following bad constant expression, We hardcode the max. number of
memory banks to four for the foreseeable future, and add an error with
instructions on what to do once it's exceeded:

fdt_support.c:397:22: error: bad constant expression

For the rest below, sparse found a couple of wrong endian conversions
in of_bus_default_translate() and fdt_get_base_address(), but
otherwise the rest is mostly annotation fixes:

fdt_support.c:64:24: warning: cast to restricted __be32
fdt_support.c:192:21: warning: incorrect type in assignment (different base types)
fdt_support.c:192:21:    expected unsigned int [unsigned] [usertype] tmp
fdt_support.c:192:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:201:21: warning: incorrect type in assignment (different base types)
fdt_support.c:201:21:    expected unsigned int [unsigned] [addressable] [usertype] tmp
fdt_support.c:201:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:304:13: warning: incorrect type in assignment (different base types)
fdt_support.c:304:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:304:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:333:13: warning: incorrect type in assignment (different base types)
fdt_support.c:333:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:333:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:359:13: warning: incorrect type in assignment (different base types)
fdt_support.c:359:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:359:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:373:21: warning: cast to restricted __be32
fdt_support.c:963:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:963:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:963:48:    got unsigned int [usertype] *<noident>
fdt_support.c:971:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:971:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:971:48:    got unsigned int [usertype] *<noident>
fdt_support.c:984:29: warning: incorrect type in argument 1 (different base types)
fdt_support.c:984:29:    expected restricted __be32 const [usertype] *cell
fdt_support.c:984:29:    got unsigned int [usertype] *addr
fdt_support.c:996:32: warning: incorrect type in argument 1 (different base types)
fdt_support.c:996:32:    expected restricted __be32 const [usertype] *cell
fdt_support.c:996:32:    got unsigned int [usertype] *addr
fdt_support.c:1041:41: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1041:41:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1041:41:    got unsigned int [usertype] *addr
fdt_support.c:1053:41: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1053:41:    expected restricted __be32 const [usertype] *range
fdt_support.c:1053:41:    got unsigned int const [usertype] *[assigned] ranges
fdt_support.c:1064:53: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1064:53:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1064:53:    got unsigned int [usertype] *addr
fdt_support.c:1110:50: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1110:50:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1110:50:    got unsigned int *<noident>
fdt_support.c:1121:49: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1121:49:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1121:49:    got unsigned int *<noident>
fdt_support.c:1147:60: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1147:60:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1147:60:    got unsigned int *<noident>
fdt_support.c:1081:5: warning: symbol '__of_translate_address' was not declared. Should it be static?
fdt_support.c:1154:5: error: symbol 'fdt_translate_address' redeclared with different type (originally declared at include/fdt_support.h:95) - incompatible argument 3 (different base types)
fdt_support.c: In function 'fdt_node_offset_by_compat_reg':
fdt_support.c:1173:17: warning: initialization discards 'const' qualifier from pointer target type [enabled by default]

See also linux kernel commit 0131d897 "of/address: use proper
endianess in get_flags".

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-07 20:38:55 -05:00
Simon Glass
67ac13b1b9 ppc: Move lbc_clk and cpu to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-04 09:04:57 -05:00
Vakul Garg
5e95e2d84b powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'
If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.

Signed-off-by: Vakul Garg <vakul@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
York Sun
2d9f26b693 powerpc/mpc85xx: Reserve default boot page
The boot page in memory is already reserved so OS won't overwrite.
As long as the boot page translation is active, the default boot page
also needs to be reserved in case the memory is 4GB or more.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Haiying Wang
990e1a8ce1 poweprc/85xx: add QMan frequency info and fdt fixup.
Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
York Sun
ffd06e0231 powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:32 -05:00
York Sun
eb53941206 powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:28 -05:00
York Sun
6d2b9da19c powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
709389b654 powerpc/mpc8xxx: fix core id for multicore booting
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Timur Tabi
055ce08004 powerpc/85xx: remove support for the Freescale P3060
The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:53 -05:00
York Sun
48f6a5c348 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
Timur Tabi
cc15df57b1 powerpc/85xx: verify the localbus device tree address before booting the OS
The localbus controller node in the device tree is typically a root node,
even though the controller is part of CCSR.  If we were to put the lbc
node under the SOC node, then the 'ranges' property in the lbc node would
translate through the 'ranges' property of the parent SOC node, and we
don't want that.

Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong.  This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
f2717b47ea powerpc/85xx: clean up and document the QE/FMAN microcode macros
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman.  Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both.  A given SOC will only have
a QE or an Fman, so this is safe.

Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND.  There's no way to know by looking at a variable how it's supposed
to be used.

In the future, the code which uploads QE firmware and Fman firmware will
be merged.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Jia Hongtao
33c875366e powerpc/85xx: fixup flexcan device tree clock-frequency
Make the fixup matchable with dts and kernel.  Update the compatible from
"fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq"
property to "clock-frequency".  We also change flexcan frequency from
CCB-clock to CCB-clock/2 according to P1010 spec.

We now keep the old interfaces to make previous kernel work. They should
be removed in the future.

Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:05 -06:00
Shengzhou Liu
f81f19fafa powerpc/85xx: Update USB device tree status based on pin settings
For P3060 and P4080, USB pins are multiplexed with other functions.
Update the device tree status for USB ports based on setting of
RCW[EC1] & RCW[EC2] which describe if pins are muxed to usb.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:37:31 -05:00
Timur Tabi
a2c1229c39 powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles
Function fdt_create_phandle() conveniently creates new phandle properties
using both "linux,phandle" and "phandle", so it should be used by all code
that wants to create a phandle.

The Fman firmware code, which embeds an Fman firmware into the device tree,
was creating the phandle properties manually.  Instead, change it to use
fdt_create_phandle().

Signed-off-by: Timur Tabi <timur@freescale.com>
2011-10-15 09:35:15 -04:00
Kumar Gala
e2d0f255cf powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
Add ifdef protection around fman specific code related to device tree
clock setup.  If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't
be executing this code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Timur Tabi
90f89f099d powerpc/85xx: verify the device tree before booting Linux
Introduce ft_verify_fdt(), a function that is called after the device tree
has been fixed up, that displays warning messages if there is a mismatch
between the physical addresses of some devices that U-Boot has configured
with what the device tree says the addresses are.

This is a particular problem when booting a 36-bit device tree from a
32-bit U-Boot (or vice versa), because the physical address of CCSR is
wrong in the device tree.  When the operating system boots, no messages are
displayed, so the user generally has no idea what's wrong.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:39 -05:00
Bhaskar Upadhaya
65bb8b060a powerpc/85xx: Fix up clock_freq property in CAN node of dts
Fix up the device tree property associated with the Flexcan clock
frequency. This property is used to calculate the bit timing parameters
for Flexcan.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:38 -05:00
Kumar Gala
acf3f8da98 powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache.  So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release.  For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:38 -05:00
Timur Tabi
ffadc441bc fman: insert the Fman firmware into the device tree
The Fman device tree node binding allows for the entire Fman firmware binary
data to be embedded in the device tree.  This eliminates the need to have
NOR flash mapped to Linux just so that the Fman driver can see the firmware.

The location of the Fman firmware is taken from the 'fman_ucode' environment
variable.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-22 03:07:43 -05:00
Timur Tabi
ee4756d4cb powerpc/85xx: fix compatible property for the L2 cache node
The compatible property for the L2 cache node (on 85xx systems that don't
have a CPC) was using a value for the property length that did not match
the actual length of the property.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-13 00:36:11 -05:00
Haiying Wang
2a0ffb84c7 powerpc/85xx: Add device tree fixup for bman portal
Fix fdt bportal to pass the bman revision number to kernel via device tree.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:03 -05:00
bhaskar upadhaya
f5feb5afb2 powerpc/85xx: Update timer-frequency prop in ptp_timer node of device tree
Fix up the device tree property associated with the IEEE 1588 timer
source frequency.  Currently we only support the IEEE 1588 timer source
being the internal eTSEC system clock (for those SoCs with IEEE 1588
support).  The eTSEC clock is ccb_clk/2.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Pankaj Chauhan
eea9a12344 powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2"
In a manner similar to passing ethernet stashing parameters into device
tree for "gianfar", extend the support to the "fsl,etsec2" as well.

Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Kumar Gala
a09b9b68d4 powerpc/8xxx: Refactor SRIO initialization into common code
Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO.  We mimic what we do with PCIe
controllers for SRIO.

We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.

We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.

Introduced the following standard defines for board config.h:

CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)

[ These mimic what we have for PCI and PCIe controllers ]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-14 01:32:21 -06:00
Aaron Sierra
9d64c6bb4a 85xx: Add support for not releasing secondary cores via 'mp_holdoff'
Some OSes require that secondary cores not be initialized when they
are booted (eg VxWorks).  By default when U-Boot is compiled with the
CONFIG_MP option all secondary cores are brought out of reset and held
in spinloops.  Setting the "mp_holdoff" environment variable to 'yes'
or '1' will cause U-Boot to leave secondary cores in their default
state.

Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-20 02:38:40 -05:00
Matthew McClintock
b80d30546e mpx85xx/fdt: Add cpu-release-addr for all cores
We currently do not add a cpu-release-addr for core 0, this is needed
when we want to reset core 0 and later restart it from Linux

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-19 21:20:10 -05:00
Kumar Gala
db977abfc8 powerpc/85xx: Add support to initialize LIODN registers and portals
On the new QorIQ/CoreNet based platforms we need to initialize the
"portals" as access into the Data Path subystem as well as Logical IO
Device Numbers (LIODN) that are used for the IOMMU (PAMU).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:56 -05:00
Kumar Gala
6aba33e939 powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platforms
The CoreNet style platforms can have a L3 cache that fronts the memory
controllers.  Enable that cache as well as add information into the
device tree about it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:56 -05:00
Kumar Gala
85f8cda3c2 powerpc/p4080: Add setting of clock-frequency for clockgen node
On QorIQ CoreNet based devices we have a global clocking block.  We want
to keep track of SYSCLK frequency as it is what is used to derive all
other frequencies in the SoC

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:18 -05:00
Kumar Gala
1b942f7483 powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates
Move to using fdt_node_offset_by_compat_reg to find the node offsets we
want to update instead of using aliases.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:40:06 -05:00
Kumar Gala
8f3a7fa4a2 powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtb
If we explicitly disabled a core remove it from the dtb we pass on to
the kernel.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:08 -05:00
Stefan Roese
a47a12becf Move arch/ppc to arch/powerpc
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-04-21 23:42:38 +02:00
Renamed from arch/ppc/cpu/mpc85xx/fdt.c (Browse further)