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3 commits

Author SHA1 Message Date
Vignesh Raghavendra
c14f3c3111 board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build 
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
 2019-05-05 08:48:50 -04:00
Lokesh Vutla
9dba883a45 board: ti: am654: r5: Add initial support for am654 
Add initial support for AM654 based EVM running on R5.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
 2018-11-16 16:51:59 -05:00
Lokesh Vutla
0911d95263 board: ti: am654: a53: Add initial support for am654 
Add initial support for AM654 based EVM running on A53. Enable
4GB of DDR available on the EVM so that kernel DTB file
can be updated accordingly.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[Andreas: Added 4GB ddr support]
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
 2018-09-11 08:32:55 -04:00